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rtl8211e-vb-cg rtl8211e-vl-cg RTL8211EG-VB-CG integrated 10/100/1000m ethernet transceiver datasheet (confidential: development partners only) rev. 1.6 03 april 2012 track id: jatr-3375-16 realtek semiconductor corp. no. 2, innovation road ii, hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211 fax: +886-3-577-6047 www.realtek.com
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver ii track id: jatr-3375-16 rev. 1. 6 copyright ?2012 realtek semiconductor corp. all rights reserve d. no part of this document may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language in any form or by any means without the written permission of realtek semiconductor corp. disclaimer realtek provides this document ?as is?, without wa rranty of any kind. realtek may make improvements and/or changes in this document or in the product de scribed in this document at any time. this document could include technical inaccuracies or typographical errors. trademarks realtek is a trademark of realtek semiconductor cor poration. other names mentioned in this document are trademarks/registered trademarks of their respective owners. license this product is covered by one or more of the following patents: us5,307,459, us5,434,872, us5,732,094, us6,570,884, us6,115,776, and us6,327,625. using this document this document is intended for the software engi neer?s reference and provides detailed programming information. though every effort has been made to ensure that th is document is current and accurate, more information may have become available subsequent to the production of this guide. revision history revision release date summary 1.0 2009/08/31 first release. 1.1 2010/08/13 added rtl8211eg-cg product data. 1.2 2010/08/16 corrected minor typing errors. 1.3 2010/12/17 added rtl8211e-vl-cg model number. revised table 23 bmcr (basic mode control register, address 0x00), page 31. revised table 32 gbcr (1000base-t contro l register, address 0x09), page 37. revised table 40 insr (interrupt status register, address 0x13), page 42. revised table 55 power sequence parameter, page 55. revised table 61 mdc/mdio management timing parameters, page 59. added section 10.6.2 mii transmission cycle timing, page 60. added section 10.6.3 mii r eception cycle timing (rtl8211e g-vb only), page 60. revised table 64 gmii timing parameters, page 62. revised ordering numbers (see table 66 ordering information, page 70).
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver iii track id: jatr-3375-16 rev. 1. 6 revision release date summary 1.4 2011/05/17 revised section 2 features, page 2. revised section 3 system applications, page 3. added section 4 block diagram, page 5. revised table 6 reset, page 11. revised table 10 power and ground, page 12. added section 7.5 interrupt, page 15. revised section 7.7 hardware configuration, page 16. revised figure 7 led and phy address configuration, page 17. revised section 7.9.2 register setting, page 18. revised section 7.10.4 manage ment interface, page 19. revised section 7.10.5 access to exte nsion page (extpage), page 21. added section 7.16 phy reset (hardware reset), page 29. revised table 23 bmcr (basic mode control register, address 0x00), page 31. revised table 37 phycr (phy specific control register, address 0x10), page 39. revised table 56 absolute maximum ratings, page 56. revised table 57 recommended operating conditions, page 56. revised table 60 dc characteristics, page 58. revised section 10.6.1 mdc/mdio timing, page 59. revised section 10.6.2 mii transmission cycle timing (rtl8211eg-vb only), page 60. revised table 66 ordering information, page 70. 1.5 2011/10/28 revised section 4 block diagram, page 5. revised table 35 maadr (mmd access addre ss data register, address 0x0e), page 39. revised table 39 iner (interrupt enable register, address 0x12), page 41. revised table 55 power sequence parameter, page 55. revised table 60 dc characteristics, page 58. revised table 62 mii transmission cycle timing, page 60. revised table 63 mii recepti on cycle timing, page 61. revised section 10.6.5 rgmii timing modes, page 63. 1.6 2012/04/03 revised table 20 register mapping and definitions, page 30. added table 22 extpage register mapping and definition, page 31. added table 42 ldpsr (link down power saving register, address 0x1b), page 42. added table 43 epagsr (extension page select register, address 0x1e), page 42. added table 51 lacr (led action control register, extpage 0x2c, address 0x1a), page 45. added table 52 lcr (led control register, extpage 0x2c, address 0x1c), page 45. added table 53 accr (auto-crossover c ontrol register, extpage 0x2d, address 0x18)45, page 45. revised section 11.4 mechanical dimensions notes (rtl8211eg-vb), page 69.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver iv track id: jatr-3375-16 rev. 1. 6 table of contents 1. general des cription............................................................................................................ ..................................1 2. features....................................................................................................................... ..................................................2 3. system applications............................................................................................................ ...................................3 3.1. a pplication d iagram (rtl8211e-vb).................................................................................................................. .3 3.2. a pplication d iagram (rtl8211eg-vb)................................................................................................................4 3.3. a pplication d iagram (rtl8211e-vl).................................................................................................................. .4 4. block diagram.................................................................................................................. .........................................5 5. pin assignments ................................................................................................................ .........................................6 5.1. rtl8211e-vb/rtl8211e-vl p in a ssignments (48-p in qfn) .............................................................................6 5.2. p ackage i dentification ............................................................................................................................... ............6 5.3. rtl8211eg-vb p in a ssignments (64-p in qfn) ....................................................................................................7 5.4. p ackage i dentification ............................................................................................................................... ............7 6. pin descriptions ............................................................................................................... .........................................8 6.1. t ransceiver i nterface ............................................................................................................................... .............8 6.2. c lock ............................................................................................................................... ..........................................8 6.3. rgmii.......................................................................................................................... ...............................................9 6.4. gmii (rtl8211eg-vb o nly ) .............................................................................................................................. ....9 6.5. m anagement i nterface ............................................................................................................................... ..........10 6.6. r eset ............................................................................................................................... .........................................11 6.7. m ode s election ............................................................................................................................... .......................11 6.8. led d efault s ettings ............................................................................................................................... ............11 6.9. r egulator and r eference ............................................................................................................................... .....12 6.10. p ower and g round ............................................................................................................................... .................12 6.11. n ot c onnected ............................................................................................................................... ........................12 7. function description ........................................................................................................... ...............................13 7.1. t ransmitter ............................................................................................................................... .............................13 7.1.1. rgmii/gmii (1000mbps) mode ..................................................................................................... .....................13 7.1.2. mii (100mbps) mode ............................................................................................................. ..............................13 7.1.3. mii (10mbps) mode .............................................................................................................. ...............................13 7.2. r eceiver ............................................................................................................................... ....................................13 7.2.1. rgmii/gmii (1000mbps) mode ..................................................................................................... .....................13 7.2.2. mii (100mbps) mode ............................................................................................................. ..............................13 7.2.3. mii (10mbps) mode .............................................................................................................. ...............................14 7.3. e nergy e fficient e thernet (eee)........................................................................................................................14 7.4. w ake -o n -lan (wol).......................................................................................................................... ..................14 7.5. i nterrupt ............................................................................................................................... ..................................15 7.6. mdi i nterface ............................................................................................................................... .........................15 7.7. h ardware c onfiguration ............................................................................................................................... .....16 7.8. led and phy a ddress c onfiguration ...............................................................................................................17 7.9. g reen e thernet (1000/100m bps m ode o nly ) .....................................................................................................18 7.9.1. cable length po wer saving ...................................................................................................... ...........................18 7.9.2. register setting............................................................................................................... ......................................18 7.10. mac/phy i nterface ............................................................................................................................... ...............19 7.10.1. mii ............................................................................................................................ .......................................19
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver v track id: jatr-3375-16 rev. 1. 6 7.10.2. gmii ........................................................................................................................... .....................................19 7.10.3. rgmii.......................................................................................................................... ....................................19 7.10.4. management interface........................................................................................................... ..........................19 7.10.5. access to extension page (extpage) ............................................................................................. ..................21 7.10.6. access to mdio manage able device (mmd)......................................................................................... ........21 7.11. a uto -n egotiation ............................................................................................................................... ...................22 7.11.1. auto-negotiation prio rity resolution........................................................................................... ...................24 7.11.2. auto-negotiation mast er/slave re solution ....................................................................................... ..............25 7.11.3. auto-negotiation pause/asymme tric pause resolution........................................................................25 7.12. c rossover d etection and a uto -c orrection ....................................................................................................26 7.13. led c onfiguration ............................................................................................................................... .................27 7.14. p olarity c orrection ............................................................................................................................... ..............28 7.15. p ower ............................................................................................................................... ........................................29 7.16. phy r eset (h ardware r eset ) .............................................................................................................................. 29 8. register de scriptions.......................................................................................................... ...............................30 8.1. r egister m apping and d efinitions .......................................................................................................................30 8.2. mmd r egister m apping and d efinition ..............................................................................................................31 8.3. e xt p age r egister m apping and d efinition ........................................................................................................31 8.4. r egister t able ............................................................................................................................... ........................31 8.4.1. bmcr (basic mode contro l register, address 0x00) ............................................................................... ..........31 8.4.2. bmsr (basic mode status register, address 0x01)................................................................................ .............33 8.4.3. phyid1 (phy identifier regi ster 1, address 0x02) ............................................................................... .............34 8.4.4. phyid2 (phy identifier regi ster 2, address 0x03) ............................................................................... .............34 8.4.5. anar (auto-negotiation advertisi ng register, address 0x04) ..................................................................... ......34 8.4.6. anlpar (auto-negotiation link partne r ability register, address 0x05) .........................................................3 5 8.4.7. aner (auto-negotiation expansi on register, address 0x06) ....................................................................... ......36 8.4.8. annptr (auto-negotiation next page transmit register, address 0x07) .........................................................36 8.4.9. annprr (auto-negotiation next page receive register, address 0x08) ...........................................................37 8.4.10. gbcr (1000base-t control register, address 0x09)............................................................................... ......37 8.4.11. gbsr (1000base-t status re gister, address 0x0a) ................................................................................ .......38 8.4.12. macr (mmd access control register, address 0x0d) ............................................................................... ..38 8.4.13. maadr (mmd access address data register, address 0x0e)......................................................................39 8.4.14. gbesr (1000base-t extended status register, address 0x0f) .....................................................................3 9 8.4.15. phycr (phy specific contro l register, a ddress 0x10)............................................................................ .....39 8.4.16. physr (phy specific status register, address 0x11)............................................................................. .......40 8.4.17. iner (interrupt enable re gister, address 0x12) ................................................................................. ...........41 8.4.18. insr (interrupt status register, address 0x13) ................................................................................. .............42 8.4.19. rxerc (receive error count er, address 0x18) .................................................................................... .........42 8.4.20. ldpsr (link down power savi ng register, address 0x1b) .......................................................................... 42 8.4.21. epagsr (extension page select register, address 0x1e) .......................................................................... ...42 8.4.22. pagsel (page select regi ster, address 0x1f) .................................................................................... ..........43 8.4.23. pc1r (pcs control 1 register, mmd device 3, address 0x00) ....................................................................43 8.4.24. ps1r (pcs status1 register, mmd device 3, address 0x01) ........................................................................ 43 8.4.25. eeecr (eee capability register, mmd device 3, address 0x14)................................................................44 8.4.26. eeewer (eee wake error register, mmd device 3, address 0x16) ..........................................................44 8.4.27. eeear (eee advertisement register, mmd device 7, address 0x3c) ..........................................................44 8.4.28. eeelpar (eee link partner ability regist er, mmd device 7, address 0x3d) ............................................44 8.4.29. lacr (led action control register , extpage 0x2c, address 0x1a)..............................................................45 8.4.30. lcr (led control register, ex tpage 0x2c, address 0x1c)......................................................................... ...45 8.4.31. accr (auto-crossover control regist er, extpage 0x2d, address 0x18).......................................................45 9. switching re gulator............................................................................................................ ..............................46 9.1. pcb l ayout ............................................................................................................................... ..............................46
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver vi track id: jatr-3375-16 rev. 1. 6 9.2. i nductor and c apacitor p arts l ist ....................................................................................................................47 9.3. m easurement c riteria ............................................................................................................................... ...........48 9.4. e fficiency m easurement ............................................................................................................................... .......54 9.5. p ower s equence ............................................................................................................................... ......................55 10. characteristics................................................................................................................ .................................56 10.1. a bsolute m aximum r atings ............................................................................................................................... ..56 10.2. r ecommended o perating c onditions .................................................................................................................56 10.3. c rystal r equirements ............................................................................................................................... ...........57 10.4. o scillator /e xternal c lock r equirements ......................................................................................................57 10.5. dc c haracteristics ............................................................................................................................... ................58 10.6. ac c haracteristics ............................................................................................................................... ................59 10.6.1. mdc/mdio timing ................................................................................................................ ........................59 10.6.2. mii transmission cycle ti ming (rtl8211eg-vb only).............................................................................. ..60 10.6.3. mii reception cycle timi ng (rtl8211eg-vb only) ................................................................................. ....61 10.6.4. gmii timing modes (rtl8211eg-vb only).......................................................................................... ........62 10.6.5. rgmii timing modes............................................................................................................. .........................63 11. mechanical dimensions.......................................................................................................... .......................66 11.1. rtl8211e-vb/rtl8211e-vl m echanical d imensions (48-p in qfn)..............................................................66 11.2. m echanical d imensions n otes (rtl8211e-vb/rtl8211e-vl) ......................................................................67 11.3. rtl8211eg-vb m echanical d imensions (64-p in qfn) ....................................................................................68 11.4. m echanical d imensions n otes (rtl8211eg-vb) .............................................................................................69 12. ordering information........................................................................................................... ........................70
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver vii track id: jatr-3375-16 rev. 1. 6 list of tables t able 1. t ransceiver i nterface ............................................................................................................................... ...............8 t able 2. c lock ............................................................................................................................... .............................................8 t able 3. rgmii .......................................................................................................................... .................................................9 t able 4. gmii (rtl8211eg-vb o nly ) .............................................................................................................................. ......9 t able 5. m anagement i nterface ............................................................................................................................... ............10 t able 6. r eset ............................................................................................................................... ............................................11 t able 7. m ode s election ............................................................................................................................... .........................11 t able 8. led d efault s ettings ............................................................................................................................... ..............11 t able 9. r egulator and r eference ............................................................................................................................... .......12 t able 10. p ower and g round ............................................................................................................................... ...................12 t able 11. n ot c onnected ............................................................................................................................... ..........................12 t able 12. config p ins vs . c onfiguration r egister ............................................................................................................16 t able 13. c onfiguration r egister d efinition ......................................................................................................................16 t able 14. m anagement f rame f ormat ............................................................................................................................... ...20 t able 15. m anagement f rame d escription ...........................................................................................................................20 t able 16. 1000b ase -t b ase and n ext p age b it a ssignments ..............................................................................................22 t able 17. led d efault d efinitions ............................................................................................................................... .........27 t able 18. led r egister t able ............................................................................................................................... ..................27 t able 19. led c onfiguration t able ............................................................................................................................... .......28 t able 20. r egister m apping and d efinitions ........................................................................................................................30 t able 21. mmd r egister m apping and d efinition ...............................................................................................................31 t able 22. e xt p age r egister m apping and d efinition ..........................................................................................................31 t able 23. bmcr (b asic m ode c ontrol r egister , a ddress 0 x 00) ......................................................................................31 t able 24. bmsr (b asic m ode s tatus r egister , a ddress 0 x 01)..........................................................................................33 t able 25. phyid1 (phy i dentifier r egister 1, a ddress 0 x 02) ...........................................................................................34 t able 26. phyid2 (phy i dentifier r egister 2, a ddress 0 x 03) ...........................................................................................34 t able 27. anar (a uto -n egotiation a dvertising r egister , a ddress 0 x 04)....................................................................34 t able 28. anlpar (a uto -n egotiation l ink p artner a bility r egister , a ddress 0 x 05) ...............................................35 t able 29. aner (a uto -n egotiation e xpansion r egister , a ddress 0 x 06)........................................................................36 t able 30. annptr (a uto -n egotiation n ext p age t ransmit r egister , a ddress 0 x 07).................................................36 t able 31. annprr (a uto -n egotiation n ext p age r eceive r egister , a ddress 0 x 08) ...................................................37 t able 32. gbcr (1000b ase -t c ontrol r egister , a ddress 0 x 09) .......................................................................................37 t able 33. gbsr (1000b ase -t s tatus r egister , a ddress 0 x 0a)..........................................................................................38 t able 34. macr (mmd a ccess c ontrol r egister , a ddress 0 x 0d) ..................................................................................38 t able 35. maadr (mmd a ccess a ddress d ata r egister , a ddress 0 x 0e) ......................................................................39 t able 36. gbesr (1000b ase -t e xtended s tatus r egister , a ddress 0 x 0f)......................................................................39 t able 37. phycr (phy s pecific c ontrol r egister , a ddress 0 x 10) ..................................................................................39 t able 38. physr (phy s pecific s tatus r egister , a ddress 0 x 11)......................................................................................40 t able 39. iner (i nterrupt e nable r egister , a ddress 0 x 12)..............................................................................................41 t able 40. insr (i nterrupt s tatus r egister , a ddress 0 x 13)...............................................................................................42 t able 41. rxerc (r eceive e rror c ounter , a ddress 0 x 18)................................................................................................42 t able 42. ldpsr (l ink d own p ower s aving r egister , a ddress 0 x 1b).............................................................................42 t able 43. epagsr (e xtension p age s elect r egister , a ddress 0 x 1e) ..............................................................................42 t able 44. pagsel (p age s elect r egister , a ddress 0 x 1f)..................................................................................................43 t able 45. pc1r (pcs c ontrol 1 r egister , mmd d evice 3, a ddress 0 x 00)........................................................................43 t able 46. ps1r (pcs s tatus 1 r egister , mmd d evice 3, a ddress 0 x 01) ...........................................................................43 t able 47. eeecr (eee c apability r egister , mmd d evice 3, a ddress 0 x 14) ...................................................................44 t able 48. eeewer (eee w ake e rror r egister , mmd d evice 3, a ddress 0 x 16).............................................................44 t able 49. eeear (eee a dvertisement r egister , mmd d evice 7, a ddress 0 x 3 c ) ...........................................................44 t able 50. eeelpar (eee l ink p artner a bility r egister , mmd d evice 7, a ddress 0 x 3 d )............................................44 t able 51. lacr (led a ction c ontrol r egister , e xt p age 0 x 2 c , a ddress 0 x 1 a ) ............................................................45
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver viii track id: jatr-3375-16 rev. 1. 6 t able 52. lcr (led c ontrol r egister , e xt p age 0 x 2 c , a ddress 0 x 1 c ) ............................................................................45 t able 53. accr (a uto -c rossover c ontrol r egister , e xt p age 0 x 2 d , a ddress 0 x 18) ...................................................45 t able 54. i nductor and c apacitor p arts l ist ......................................................................................................................47 t able 55. p ower s equence parameter ............................................................................................................................... ....55 t able 56. a bsolute m aximum r atings ............................................................................................................................... ...56 t able 57. r ecommended o perating c onditions ...................................................................................................................56 t able 58. c rystal r equirements ............................................................................................................................... .............57 t able 59. o scillator /e xternal c lock r equirements ........................................................................................................57 t able 60. dc c haracteristics ............................................................................................................................... ..................58 t able 61. mdc/mdio m anagement t iming p arameters ....................................................................................................59 t able 62. mii t ransmission c ycle t iming .............................................................................................................................60 t able 63. mii r eception c ycle t iming ............................................................................................................................... ....61 t able 64. gmii t iming p arameters ............................................................................................................................... .........62 t able 65. rgmii t iming p arameters ............................................................................................................................... .......65 t able 66. o rdering i nformation ............................................................................................................................... .............70
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver ix track id: jatr-3375-16 rev. 1. 6 list of figures f igure 1. a pplication d iagram (rtl8211e-vb).................................................................................................................. ..3 f igure 2. a pplication d iagram (rtl8211eg-vb)................................................................................................................. 4 f igure 3. a pplication d iagram (rtl8211eg-vl)................................................................................................................. 4 f igure 4. b lock d iagram ............................................................................................................................... ...........................5 f igure 5. rtl8211e-vb/rtl8211e-vl p in a ssignments (48-p in qfn) ..............................................................................6 f igure 6. rtl8211eg-vb p in a ssignments (64-p in qfn) .....................................................................................................7 f igure 7. led and phy a ddress c onfiguration ................................................................................................................17 f igure 8. mdc/mdio r ead t iming ............................................................................................................................... .........20 f igure 9. mdc/mdio w rite t iming ............................................................................................................................... ........21 f igure 10. phy r eset t iming ............................................................................................................................... .....................29 f igure 11. s witching r egulator ............................................................................................................................... ..............46 f igure 12. i nput v oltage o vershoot <4v (g ood )................................................................................................................48 f igure 13. i nput v oltage o vershoot >4v (b ad ) ..................................................................................................................48 f igure 14. c eramic 10 f 0603 (x5r) (g ood ) ..........................................................................................................................49 f igure 15. l=glk2510p-2r2m, c=c eramic 4.7 f 0805 x5r tdk (r ipple 12.4 m v) ...........................................................49 f igure 16. l=glk2510p-2r2m, c=c eramic 10 f 0603 x5r yageo (r ipple 13.2 m v) ......................................................50 f igure 17. l=glk2510p-4r7m, c=c eramic 4.7 f 0805 x5r tdk (r ipple 12 m v) ..............................................................50 f igure 18. l=glk2510p-4r7m, c=c eramic 10 f 0603 x5r yageo (r ipple 11.2 m v) ......................................................51 f igure 19. l=gtsd32p-2r2m, c=c eramic 4.7 f 0805 x5r tdk (r ipple 9.2 m v)...............................................................51 f igure 20. c eramic 10 f (y5v) (b ad ).............................................................................................................................. ........52 f igure 21. e lectrolytic 100 f (r ipple t oo h igh ).................................................................................................................52 f igure 22. gtsd32p-2r2m (g ood ).............................................................................................................................. ............53 f igure 23. 1 h b ead (b ad ).............................................................................................................................. ..........................53 f igure 24. s witching r egulator e fficiency m easurement c heckpoint ..........................................................................54 f igure 25. p ower s equence ............................................................................................................................... .......................55 f igure 26. mdc/mdio s etup , h old t ime , and v alid from mdc r ising e dge t ime d efinitions ....................................59 f igure 27. mdc/mdio m anagement t iming p arameters ...................................................................................................59 f igure 28. mii i nterface s etup /h old t ime d efinitions .......................................................................................................60 f igure 29. mii t ransmission c ycle t iming ............................................................................................................................60 f igure 30. mii r eception c ycle t iming ............................................................................................................................... ...61 f igure 31. gmii t iming ............................................................................................................................... ..............................62 f igure 32. rgmii t iming m odes (f or txc) ........................................................................................................................... 63 f igure 33. rgmii t iming m odes (f or rxc) ........................................................................................................................... 64
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 1 track id: jatr-3375-16 rev. 1. 6 1. general description the realtek rtl8211e-vb-cg/rtl8211e-vl-cg/rtl8211e g-vb-cg are highly integrated ethernet transceivers that comply with 10base-t, 100b ase-tx, and 1000base-t ieee 802.3 standards. they provide all the necessary physical layer functions to transmit and receive ethernet packets over cat.5 utp cable. the rtl8211e-vb(vl)/rtl8211eg-vb uses state-of-t he-art dsp technology and an analog front end (afe) to enable high-speed data transmission and r eception over utp cable. functions such as crossover detection & auto-correction, polarity correction, ad aptive equalization, cross-talk cancellation, echo cancellation, timing recovery, and error correction are implemented in the rtl8211e-vb(vl)/rtl8211eg-vb to provide robus t transmission and reception capabilities at 10mbps, 100mbps, or 1000mbps. data transfer between mac and phy is via the re duced gigabit media independent interface (rgmii) or gigabit media independent interface (gmii) fo r 1000base-t, 10base-t, and 100base-tx. the rtl8211e-vb and rtl8211eg-vb support 3.3v or 2.5v signaling for rgmii/gmii. the rtl8211e-vl supports 1.5/1.8v signaling for rgmii.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 2 track id: jatr-3375-16 rev. 1. 6 2. features ? 1000base-t ieee 802.3ab compliant ? 100base-tx ieee 802.3u compliant ? 10base-t ieee 802.3 compliant ? supports rgmii (rtl8211e-vb, rtl8211e-vl, rtl8211eg-vb) ? supports gmii (rtl8211eg-vb) ? supports ieee 802.3az-2010 (energy efficient ethernet) ? built-in wake-on-lan (wol) ? supports interrupt function ? supports parallel detection ? crossover detection & auto-correction ? automatic polarity correction ? supports phyrstb core power turn-off ? baseline wander correction ? supports 120m for cat.5 cable in 1000base-t ? supports 3.3v or 2.5v signaling for rgmii/gmii (rtl8211e-vb, rtl8211eg-vb) ? supports 1.5v and 1.8v signaling for rgmii (rtl8211e-vl) ? supports 25/50mhz external crystal or osc ? provides 125mhz clock source for mac ? provides 3 network status leds ? supports link down power saving ? green ethernet (1000/100mbps mode only) ? built-in switching regulator ? packages ? 48-pin qfn (rtl8211e-vb, rtl8211e-vl) ? 64-pin qfn (rtl8211eg-vb) ? 0.11m process with very low power consumption
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 3 track id: jatr-3375-16 rev. 1. 6 3. system applications ? dtv (digital tv) ? mau (media access unit) ? cnr (communication and network riser) ? game console ? printer and office machine ? dvd player and recorder ? ethernet hub ? ethernet switch in addition, can be used in any embedded system with an ethernet mac that needs a utp physical connection. 3.1. application diagram (rtl8211e-vb) figure 1. application diagram (rtl8211e-vb)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 4 track id: jatr-3375-16 rev. 1. 6 3.2. application diagram (rtl8211eg-vb) figure 2. application diagram (rtl8211eg-vb) 3.3. application diagram (rtl8211e-vl) figure 3. application diagram (rtl8211eg-vl)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 5 track id: jatr-3375-16 rev. 1. 6 4. block diagram figure 4. block diagram
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 6 track id: jatr-3375-16 rev. 1. 6 5. pin assignments 5.1. rtl8211e-vb/rtl8211e-vl pin assignments (48-pin qfn) figure 5. rtl8211e-vb/rtl8211e-v l pin assignments (48-pin qfn) 5.2. package identification green package is indicated by the ?g? in gxxxv (figure 5). the version is shown in the location marked ?v?.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 7 track id: jatr-3375-16 rev. 1. 6 5.3. rtl8211eg-vb pin assignments (64-pin qfn) dvdd 33 led1 / phy_ ad1 led2 rxd 3 txer gnd vddreg ckxtal2 ckxtal1 avdd33 avdd10 led0 /phy_ ad0 mdc enswreg pmeb intb mdio rxdv/phy_ad2 rset dvdd10 txd5 txd4 txclk txd3 txd1 dv d d 3 3 txd2 phyr st b txd0 gt x _c l k txd7 dvdd10 txd6 rxd 1 rxd2 rxd0 dvdd 33 rxc rxd4 / selrgv dvdd33 rxd5/txdly rxd6/rxdly rxd7 / an0 rxer / an1 txen col/mode nc crs reg_ou t mdi[0]+ mdi avdd10 mdi mdi avdd33 mdi avdd10 mdi mdi nc gnd gnd cl k125 mdi 1 2 3 4 5 6 78 9 10 11 12 36 35 34 33 56 55 54 53 49 50 51 52 60 59 58 57 13 14 15 16 17 18 19 20 24 23 22 21 25 26 27 28 29 30 31 32 40 39 38 37 41 43 42 47 46 45 44 48 64 63 62 61 65 gnd (exposed pad) [0]- [1]+ [1]- [2]+ [2]- [3]+ [3]- figure 6. rtl8211eg-vb pin assignments (64-pin qfn) 5.4. package identification green package is indicated by the ?g? in gxxxv (figure 6). the version is shown in the location marked ?v?.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 8 track id: jatr-3375-16 rev. 1. 6 6. pin descriptions note that some pins have multiple functions. refer to the pin assignments figure on page 6 (rtl8211e-vb/rtl8211e-vl) and page 7 (rtl 8211eg-vb) for a graphical representation. i: input li: latched input during power up or reset o: output io: bi-directional input and output p: power pd: internal pull down during power on reset pu: internal pull up during power on reset od: open drain g: ground 6.1. transceiver interface table 1. transceiver interface pin no. (48-pin) pin no. (64-pin) pin name type description 1 5 mdi[0]+ io 2 6 mdi[0] ? io in mdi mode, this is the first pair in 1000base-t, i.e., the bi_da+/- pair, and is the transmit pair in 10base-t and 100base-tx. in mdi crossover mode, this pair acts as the bi_db+/- pair, and is the receive pair in 10base-t and 100base-tx. 4 8 mdi[1]+ io 5 9 mdi[1] ? io in mdi mode, this is the second pair in 1000base-t, i.e., the bi_db+/- pair, and is the receive pair in 10base-t and 100base-tx. in mdi crossover mode, this pair acts as the bi_da+/- pair, and is the transmit pair in 10base-t and 100base-tx. 7 11 mdi[2]+ io 8 12 mdi[2] ? io in mdi mode, this is the third pair in 1000base-t, i.e., the bi_dc+/- pair. in mdi crossover mode, this pair acts as the bi_dd+/- pair. 10 14 mdi[3]+ io 11 15 mdi[3] ? io in mdi mode, this is the fourth pair in 1000base-t, i.e., the bi_dd+/- pair. in mdi crossover mode, this pair acts as the bi_dc+/- pair. 6.2. clock table 2. clock pin no. (48-pin) pin no. (64-pin) pin name type description 42 61 ckxtal1 i 25/50mhz crystal input. if a 25/50mhz oscillator is used, connect ckxtal1 to the oscillator?s output (see section 10.3, page 57 for clock source specifications). 43 62 ckxtal2 o 25/50mhz crystal output. connect to gnd if an external 25/ 50mhz oscillator drives ckxtal1. 46 1 clk125 o/pd 125mhz reference clock generated from internal pll. this pin should be kept floating if the 125mhz clock is not used by mac. note: for those who conduct crystal ppm measurement for the models transited from rtl8211d to rtl8211e, note that the design of external circuit shall be modified, i.e. the output resistor shoul d be connected to ckxtal1 rather than ckxtal2.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 9 track id: jatr-3375-16 rev. 1. 6 6.3. rgmii table 3. rgmii pin no. (48-pin) pin no. (64-pin) pin name type (48-pin) type (64-pin) description 22 - txc i/pu - 34 gtx_clk i the transmit reference clock will be 125mhz, 25mhz, or 2.5mhz depending on speed. 23 36 txd0 i/pd 24 39 txd1 i/pd 25 40 txd2 i/pd 26 41 txd3 i/pu transmit data. data is transmitted from mac to phy via txd[3:0]. 27 - txctl - 35 txen i receive control signal from the mac. 19 24 rxc o the continuous receive reference clock will be 125mhz, 25mhz, or 2.5mhz, and is de rived from the received data stream. 14 19 rxd0 o/li/pu o 16 21 rxd1 o/li/pd o 17 22 rxd2 o/li/pu o 18 23 rxd3 o/li/pu o receive data. data is transmitted from phy to mac via rxd[3:0]. 13 - rxctl - 18 rxdv o/li/pd transmit control signal to the mac. 16 27 txdly o/li/pd rgmii transmit clock timing control. 1: add 2ns delay to txc for txd latching 32 28 rxdly o/li/pd rgmii recei ver clock timing control. 1: add 2ns delay to rxc for rxd latching 6.4. gmii (rtl8211eg-vb only) table 4. gmii (rtl8211eg-vb only) pin no. (48-pin) pin no. (64-pin) pin name type description - 34 gtx_clk i the transmit reference clock is 125mhz. - 42 txclk o the transmit reference clock will be 25mhz, or 2.5mhz depending on speed. - 36 txd0 i - 39 txd1 i - 40 txd2 i - 41 txd3 i - 43 txd4 i - 44 txd5 i - 45 txd6 i - 46 txd7 i transmit data. data is transmitted from mac to phy via txd[7:0]. - 35 txen i transmit enable.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 10 track id: jatr-3375-16 rev. 1. 6 pin no. (48-pin) pin no. (64-pin) pin name type description - 47 txer i transmit error. when both txer and txen are assert ed, the transmit error symbol is transmitted onto the cable. when txer is asserted and txen is de-asserted, the carrier extension symbol is transmitted onto the cable. connect to gnd if mac does not have a txer pin. - 24 rxc o the continuous receive refe rence clock will be 125mhz, 25mhz, or 2.5mhz. it is derived from the received data stream. - 19 rxd0 o - 21 rxd1 o - 22 rxd2 o - 23 rxd3 o - 25 rxd4 o/li/pu - 27 rxd5 o/li/pd - 28 rxd6 o/li/pd - 29 rxd7 o/li/pu receive data. data is transmitted from phy to mac via rxd[7:0]. - 18 rxdv o/li/pd receive data valid. - 30 rxer o/li/pu receive error. when both rxer and rxdv are assert ed, an error symbol is received from the cable. when rxer is asserted and rxdv is de-asserted, it means false carrier or carrier extension symbol is detected on the cable. - 31 col/mode o/li/pd collision in half duplex mode. - 32 crs o/pd carrier sense. 6.5. management interface table 5. management interface pin no. (48-pin) pin no. (64-pin) pin name type description 30 53 mdc i/pu management data clock. 31 54 mdio io/pu input/output of management data. pull up 3.3v for 3.3v rgmii (rtl8211e/eg-vb) & gmii (rtl8211eg-vb). pull up 2.5v for 2.5v rgmii (rtl8211e/eg-vb) & gmii (rtl8211eg-vb). pull up 1.5/1.8v for 1.5/1.8v rgmii (rtl8211e-vl). 33 55 pmeb o/od power management event (supports 3.3v and 5v pull up). set low if received a magic packet or wake up frame; active low. this pin will be kept floating if this function is not used. 20 56 intb o/od interrupt. set low if status changed; active low. this pin will be kept floating if this function is not used.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 11 track id: jatr-3375-16 rev. 1. 6 6.6. reset table 6. reset pin no. (48-pin) pin no. (64-pin) pin name type description 29 38 phyrstb i hardware reset. active low. for a complete phy reset, this pin must be asserted low for at least 10ms. all registers will be cleared after a hardware reset. 6.7. mode selection table 7. mode selection pin no. (48-pin) pin no. (64-pin) pin name type (48-pin) type (64-pin) description 34 50 phy_ad0 o/li/pu 35 51 phy_ad1 o/li/pd 13 18 phy_ad2 o/li/pd phy address configuration. 17 29 an0 o/li/pu 18 30 an1 o/li/pu auto-negotiation (nway) configuration. - 31 col/mode - o/li/pd rgmii/gmii mode configuration. pull up for rgmii. pull down for gmii. 14 25 selrgv o/li/pu pull up for 3.3v rgmii (rtl8211e/eg-vb) & gmii (rtl8211eg-vb). pull down for 2.5v rgmii (rtl8211e/eg-vb) & gmii (rtl8211eg-vb). pull up for 1.5/1.8v rgmii (rtl8211e-vl). note: for thertl8211e-vl, selrgv should not be pulled down. note: see section 7.7 hardware configuration, page 16 for details. 6.8. led default settings table 8. led default settings pin no. (48-pin) pin no. (64-pin) pin name type description 34 50 led0 o/li/pu blinking= transmitting or receiving. 35 51 led1 o/li/pd low=link up (any speed) high=link down (any speed) note: high/low active depends on hardware configuration setting. 32 52 led2 o/li/pd no default setting. see table 19 led configuration table, page 28 for configuration details. note: see section 7.13 led configuration, page 27 for details.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 12 track id: jatr-3375-16 rev. 1. 6 6.9. regulator and reference table 9. regulator and reference pin no. (48-pin) pin no. (64-pin) pin name type description 39 58 rset o reference. external resistor reference. 44, 45 64 vddreg p analog 3.3v power supply for switching regulator. 48 3 reg_out o switching regulator 1.05v output. connect to a 2.2h or 4.7h inductor. 3 7 avdd10 p feedback pin for switching regulator. 38 57 enswreg i 3.3v: enable switching regulator 0v: disable switching regulator 6.10. power and ground table 10. power and ground pin no. (48-pin) pin no. (64-pin) pin name type description 37 49 dvdd33 p digital power 3.3v. 15, 21 20, 26, 37 dvdd33 p digital io power (3.3/2.5/1.8/1.5v) connect to 3.3v for 3.3v rgm ii i/o (rtl8211e/eg-vb) & gmii i/o (rtl8211eg-vb). connect to 2.5v for 2.5v rgm ii i/o (rtl8211e/eg-vb) & gmii i/o (rtl8211eg-vb). connect to 1.5/1.8v for 1.5/1.8v rgmii i/o (rtl8211e-vl). 28, 36 33, 48 dvdd10 p digital power. 1.05v. 6, 41 10, 60 avdd33 p analog power. 3.3v. 44,45 64 vddreg p analog 3.3v power supply for switching regulator. 3, 9, 40 7, 13, 59 avdd10 p analog power. 1.05v. 47 2, 4, 63 gnd g ground. exposed pad (e-pad) is analog and digital ground (see section 11 mechanical dimensions, page 66). 6.11. not connected table 11. not connected pin no. (48-pin) pin no. (64-pin) pin name type description 12 16, 17 nc - not connected.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 13 track id: jatr-3375-16 rev. 1. 6 7. function description 7.1. transmitter 7.1.1. rgmii/gmii (1000mbps) mode the rtl8211e-vb(vl)/rtl8211eg-vb?s pcs layer r eceives data bytes from the mac through the rgmii/gmii interface and performs generation of continuous code-groups through 4d-pam5 coding technology. these code groups are passed through a wave form-shaping filter to minimize emi effect, and are transmitted onto the 4-pair cat.5 cable at 125mbaud/s through a d/a converter. 7.1.2. mii (100mbps) mode the transmitted 4-bit nibbles (txd[3:0]) from the mac, clocked at 25mhz (txclk), are converted into 5b symbol code through 4b/5b c oding technology, then through scrambling and serializing, are converted to 125mhz nrz and nrzi signals. the nrzi signals ar e passed to the mlt3 encoder, then to the d/a converter and transmitted onto the media. 7.1.3. mii (10mbps) mode the transmit 4-bit nibbles (txd[3:0] ) from the mac, clocked at 2.5mhz (txclk), are serialized into 10mbps serial data. the 10mbps serial data is convert ed into a manchester-encoded data stream and is transmitted onto the media by the d/a converter. 7.2. receiver 7.2.1. rgmii/gmii (1000mbps) mode input signals from the media first pass through the on-chip sophisticated hybrid circuit to subtract the transmitted signal from the input signal for effectiv e reduction of near-end echo. afterwards, the received signal is processed with state-of-the-art tec hnology, such as adaptive equalization, blw (baseline wander) correction, cross-talk cancellation, echo cancellation, timing recovery, error correction, and 4d-pam5 decoding. the 8-bit-wide data is recovered and is sent to the rgmii/gmii interface at a clock speed of 125mhz. the rx mac retrieves the packet data from the receive rgmii/gmii interface and sends it to the rx buffer manager. 7.2.2. mii (100mbps) mode the mlt3 signal is processed with an adc, equalizer, blw (baseline wander) correction, timing recovery, mlt3 and nrzi decoder, descrambler, 4b/5b decoder, and is then presented to the mii interface in 4-bit-wide nibbles at a clock speed of 25mhz.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 14 track id: jatr-3375-16 rev. 1. 6 7.2.3. mii (10mbps) mode the received differential signal is converted into a ma nchester-encoded stream first. next, the stream is processed with a manchester decoder, and is de-seria lized into 4-bit-wide nibbles. the 4-bit nibbles are presented to the mii interface at a clock speed of 2.5mhz. 7.3. energy efficient ethernet (eee) the rtl8211e-vb(vl)/rtl8211eg-vb supports i eee 802.3az-2010, also known as energy efficient ethernet (eee), at 10mbps, 100mbps, and 1000mbps. it pr ovides a protocol to coordinate transitions to/from a lower power consumption level (low po wer idle mode) based on link utilization. when no packets are being transmitted, the system goes to low power idle mode to save power. once packets need to be transmitted, the system returns to normal mode , and does this without ch anging the link status and without dropping/corrupting frames. to save power, when the system is in low power idle mode, most of the circuits are disabled, however, the transition time to/from low power idle mode is kept small enough to be transparent to upper layer protocols and applications. eee also specifies a negotiation method to enable link partners to determine whether eee is supported. refer to http://www.ieee802.org/3/az/index.html for more details. 7.4. wake-on-lan (wol) the rtl8211e-vb(vl)/rtl8211eg-vb can monitor the network for a wakeup frame or a magic packet, and notify the system via the pmeb (power management event; ?b? means low active) pin when such a packet or event occurs. the system can then be restored to a normal state to process incoming jobs. the pmeb pin needs to be connected with a 4.7k-ohm resistor and pulled up to 3.3v or 5v. when the wakeup frame or a magic packet is sent to the phy, the pmeb pin will be set lo w to notify the system to wake up. refer to the wol application note for details. magic packet wakeup occurs only when the following conditions are met: ? the destination address of the received magic packet is acceptable to the rtl8211e-vb(vl)/rtl8211eg-vb, e.g., a broadcast, multicast, or unicast packet addressed to the current rtl8211e-vb(vl)/rtl8211eg-vb. ? the received magic packet does not contain a crc error. ? the magic packet pattern matches; i.e., 6 * ffh + misc (can be none) + 16 * did (destination id) in any part of a valid ethernet packet.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 15 track id: jatr-3375-16 rev. 1. 6 a wakeup frame event occurs only when the following conditions are met: ? the destination address of the received wakeup frame is acceptable to the rtl8211e-vb(vl)/rtl8211eg-vb, e.g., a broadcast, multicast, or unicast address to the current rtl8211e-vb(vl)/rtl8211eg-vb. ? the received wakeup frame does not contain a crc error. ? the 16-bit crc* of the received wakeup frame matc hes the 16-bit crc of the sample wakeup frame pattern given by the local machine?s os. or, the r tl8211e-vb(vl)/rtl8211eg-vb is configured to allow direct packet wakeup, e.g., a broadcast, multicast, or unicast network packet. note: 16-bit crc: the rtl8211e-vb(vl)/rtl8211e g-vb supports eight long wakeup frames (covering 128 mask bytes from offset 0 to 127 of any incoming network packet). crc16 polynomial=x 16 +x 12 +x 5 +1. 7.5. interrupt whenever there is a status change on the me dia detected by the rtl8211e-vb(vl)/rtl8211eg-vb, they will drive the interrupt pin (intb ) low to issue an interrupt event. the mac senses the status change and accesses the registers (page 0, register 19) through the mdc/mdio interface in response. once these status registers (page 0, register 19) ha ve been read by the mac through the mdc/mdio, the intb is de-asserted. the rtl8211e-vb(vl)/rtl8211e g-vb interrupt function removes the need for continuous polling through the mdc/mdio management interface. 7.6. mdi interface this interface consists of four signal pairs; mdi0, mdi1, mdi2, and mdi3. each signal pair consists of two bi-directional pins that can transmit and receive at the same time. the mdi interface has internal termination resistors to reduce bom cost and pcb comp lexity. for 1000base-t, all four pairs are used in both directions at the same time. for 10/100 links a nd during auto-negotiation, onl y pairs a and b are used.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 16 track id: jatr-3375-16 rev. 1. 6 7.7. hardware configuration the operation speed, interface mode, and phy address can be set by the config pins. the respective value mapping of config with the configurable vector is listed in table 12. to set the config pins, an external pull-high or pull-low via resistor is required. table 12. config pins vs. configuration register rtl8211e-vb(vl) pin rtl8211eg-vb pin pin name led0 led0 phyad[0] led1 led1 phyad[1] rxctl rxdv phyad[2] rxd2 rxd7 an[0] rxd3 rxer an[1] - col mode led2 rxd6 rx delay rxd1 rxd5 tx delay rxd0 rxd4 selrgv table 13. configuration register definition configuration description phyad[2:0] phy address. phyad sets the phy address for the device. the rtl8211e-vb(vl)/rtl8211eg-vb support phy addresses from 00001 to 00111. phy address 0 is a broadcast from the mac; each phy device should respond. note: phyad[2:0]=000 can support all phy addresses. it can automatically remember the first non-zero phy address. an[1:0] auto-negotiation (nway) configuration. an[1:0] controls the auto-nego tiation speed and duplex settings. 00: 10base-t full/half duplex 01: 100base-tx half duplex ; 10base-t full/half duplex 10: 100base-tx full/half duplex ; 10base-t full/half duplex 11: nway. advertise all capabilities (10/ 1000base-t; 100base-tx full/half duplex) mode interface mode select. 0: mii/gmii (via 4.7k-ohm to gnd) 1: rgmii (via 4.7k-ohm to 3.3v) note: ?mode? specifies the rtl8211eg-vb operating mode. rx delay rgmii transmit clock timing control. 1: add 2ns delay to rxc for rxd latching (via 4.7k-ohm to 3.3v) 0: no delay (via 4.7k-ohm to gnd) tx delay rgmii transmit clock timing control. 1: add 2ns delay to txc for txd latching (via 4.7k-ohm to 3.3v) 0: no delay (via 4.7k-ohm to gnd) selrgv 3.3v or 2.5v rgmii/gmii selection. 1: 3.3v rgmii/gmii (rtl8211e-vb & rtl8211eg-vb) 1.5/1.8v rgmii (rtl8211e-vl) 0: 2.5v rgmii/gmii (rtl8211e-vb & rtl8211eg-vb) note: for the rtl8211e-vl, selrgv should not be pulled down.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 17 track id: jatr-3375-16 rev. 1. 6 7.8. led and phy address configuration in order to reduce the pin count on the rtl8211e -vb(vl)/rtl8211eg-vb, the led pins are duplexed with the phy address pins. as the phyad strap options share the led output pins, the external combinations required for strapping and led usage mu st be considered in order to avoid contention. specifically, when the led outputs are used to drive led s directly, the active state of each output driver is dependent on the logic level sampled by the corresponding phyad input upon power-up/reset. for example, as figure 7 (left-side) shows, if a gi ven phyad input is resistiv ely pulled high then the corresponding output will be configured as an active low dr iver. on the right side, we can see that if a given phyad input is resistively pulled low then the corre sponding output will be configured as an active high driver. the phy address configurati on pins should not be connected to gnd or vcc directly, but must be pulled high or low through a resistor (e.g., 4.7k ? ). if no led indications are needed, the components of the led path (led+510 ? ) can be removed. phy address[:]=logical 1 phy address[:]=logical 0 rxdly=logical 1 rxdly=logical 0 led indication=active low led indication=active high figure 7. led and phy address configuration
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 18 track id: jatr-3375-16 rev. 1. 6 7.9. green ethernet (1000/100mbps mode only) 7.9.1. cable length power saving in 1000/100mbps mode the rtl8211e-vb(vl)/rtl8211e g-vb provides dynamic detection of cable length and dynamic adjustment of power required for the detected cable length. this feature provides intermediate performance with minimum power consumption. 7.9.2. register setting follow the register settings below to disabl e green ethernet (default is ?enabled?) write reg31, data=0x0003 (page3) write reg25, data=0x3246 write reg16, data=0xa87c write reg31, data=0x0000 (page0) follow the register settings below to enable green ethernet (default is ?enabled?) write reg31, data=0x0003 (page3) write reg25, data=0x3247 write reg16, data=0xac7c write reg31, data=0x0000 (page0)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 19 track id: jatr-3375-16 rev. 1. 6 7.10. mac/phy interface the rtl8211e-vb/rtl8211e-vl supports industry standa rds and is suitable for most off-the-shelf macs with an rgmii interface. the rtl8211eg-vb supports industry standards and is suitable for most off-the-shelf macs with gmii and rgmii interfaces. 7.10.1. mii in 100base-tx and 10base-t modes (mii mode is selected), txc and rxc sources are 25mhz and 2.5mhz respectively. txc and rxc will always be generated by the phy. txd[3:0] and rxd[3:0] signals are used for data transitions. 7.10.2. gmii in 1000base-t mode (gmii interface is selected), a 125mhz transmit clock is expected on gtx_clk. rxclk sources the 125mhz receive clock. 7.10.3. rgmii in 1000base-t mode (rgmii interface is selected), txc and rxc sources are 125mhz. txc will always be generated by the mac and rxc will always be gene rated by the phy. txd[3:0] and rxd[3:0] signals are used for data transitions on rising edge and on falling edge of clock. 7.10.4. management interface the management interface provides access to the intern al registers through the mdc and mdio pins as described in ieee 802.3u section 22. the mdc signal, provided by the mac, is the management data clock reference to the mdio signal. the mdio is the management data input/output and is a bi-directional signal that runs synchronously to mdc. the mdio pi n needs a 1.5k ohm pull-up resistor to maintain the mdio high during idle and turnaround. preamble suppression is the default setting of the rtl8211e-vb(vl)/rtl 8211eg-vb after power-on. however, there still must be at least one idle bit between operations. the rtl8211e-vb(vl)/rtl8211eg-vb can share the same mdio line. in switch/router applications, each port should be assigned a unique address during the hardware reset sequence, and it can only be addressed via that unique phy address. for detailed information on the rtl8211e-vb(vl)/rtl8211eg-vb management registers, see section 8 register descriptions, page 30.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 20 track id: jatr-3375-16 rev. 1. 6 table 14. management frame format management frame fields preamble st op phyad regad ta data idle read 1?1 01 10 aaaaa rrrrr z0 dddddddddddddddd z write 1?1 01 01 aaaaa rrrrr 10 dddddddddddddddd z table 15. management frame description name description preamble 32 contiguous logical 1?s sent by the mac on mdio, along with 32 corresponding cycles on mdc. this provides synchronization for the phy. st start of frame. indicated by a 01 pattern. op operation code. read: 10 write: 01 phyad phy address. up to eight phys can be connected to one mac. this 3-bit field selects which phy the frame is directed to. regad register address. this is a 5-bit field that sets which of the 32 registers of the phy this operation refers to. ta turnaround. this is a 2-bit-time spacing between the register address and the data field of a frame to avoid contention during a read transaction. for a read transaction, bot h the sta and the phy remain in a high-impedance state for the first bit time of the turnaround. the phy drives a zero bit during the second bit time of the turnaround of a read transaction. data data. these are the 16 bits of data. idle idle condition. not truly part of the management frame. this is a high impedance state. electrically, the phy?s pull-up resistor will pull the mdio line to a logical ?1?. figure 8. mdc/mdio read timing
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 21 track id: jatr-3375-16 rev. 1. 6 0 1 0 0000 00000 0000 00 0 00000 1 1 111 z write op (code) phy address 0x01 reg. address 0x00(bmcr) turn around reg. data 0x 1340 idle 1 1 z 0 start mdc mdio(mac) pre 1...1 figure 9. mdc/mdio write timing 7.10.5. access to extension page (extpage) set mdio commands as shown below to switch to the extension page (extpage) 0xxy (in hex). 1. write register 31 data=0x0007 (set to extension page) 2. write register 30 data=0x00xy (extension page xy) 3. write the target register data 4. write register 31 data=0x0000 (switch to page 0) 7.10.6. access to mdio manageable device (mmd) the mdio manageable device (mmd) is an extensi on to the management interface that provides the ability to access more device registers while still retain ing logical compatibility with the mdio interface, defined in section 8.1 register mapping and definitions, page 30. access to mmd configuration is provided via registers 13 and 14. mmd read/write operation 1. write function field to 00 (addre ss mode) and devad field to the device address value for the desired mmd (register 13). 2. write the desired address value to the mmd?s address register (register 14). 3. write function field to 01 (data mode; no post increm ent) and devad field to the same device address for the desired mmd (register 13). 4. read: go to step 5. write: go to step 6. 5. read the content of the selected register in mmd (register 14). 6. write the content of the selected register in mmd (register 14).
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 22 track id: jatr-3375-16 rev. 1. 6 7.11. auto-negotiation auto-negotiation is a mechanism to determine the fa stest connection between two link partners. for copper media applications, it was introduced in ieee 802.3u fo r ethernet and fast ethernet, and then in ieee 802.3ab to address extended functions for gi gabit ethernet. it performs the following: ? auto-negotiation priority resolution ? auto-negotiation master/slave resolution ? auto-negotiation pause/asymmetric pause resolution ? crossover detection & auto-correction resolution upon de-assertion of a hardware reset, the rtl 8211e-vb(vl)/rtl8211eg-vb can be configured to have auto-negotiation enabled, or be set to operate in 10base-t, 100base-tx, or 1000base-t mode via the config pins (see section 7.7 hardware configuration, page 16). the auto-negotiation process is initiated automatically upon any of the following: ? power-up ? hardware reset ? software reset (register 0.15) ? restart auto-negotiation (register 0.9) ? transition from power down to power up (register 0.11) ? entering the link fail state table 16. 1000base-t base and next page bit assignments bit name bit description register location base page d15 np next page. 1: indicates that next pages follow 0: indicates that no next pages follow - d14 ack acknowledge. 1: indicates that a device ha s successfully received its link partner?s link code word (lcw) - d13 rf remote fault. 1: indicates to its link partner that a device has encountered a fault condition - d[12:5] a[7:0] tec hnology ability field. indicates to its link partner the supported technologies specific to the selector field value. register 4.[12:5] table 27, page 34. d[4:0] s[4:0] selector field. always 00001. indicates to its link partner th at it is an ieee 802.3 device. register 4.[4:0] table 27, page 34.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 23 track id: jatr-3375-16 rev. 1. 6 bit name bit description register location page 0 (message next page) m15 np next page. 1: indicates that next pages follow 0: indicates that no next pages follow - m14 ack acknowledge. 1: indicates that a device ha s successfully received its link partner?s link code word (lcw) - m13 mp message page. 1: indicates to its link partner that this is a message page, not an unformatted page. - m12 ack2 acknowledge 2. 1: indicates to its link partner that the device has the ability to comply with the message. - m11 t toggle. used by the nway arbitration function to ensure synchronization with its link partner during next page exchange. - m[10:0] - 1000base-t message code (always 8). - page 1 (unformatted next page) u15 np next page. 1: indicates that next pages follow 0: indicates that no next pages follow - u14 ack acknowledge. 1: indicates that a device ha s successfully received its link partner?s link code word (lcw) - u13 mp message page. 1: indicates to its link partner that this is a message page, not an unformatted page. - u12 ack2 acknowledge 2. 1: indicates to its link partner that the device has the ability to comply with the message. - u11 t toggle. used by the nway arbitration function to ensure synchronization with its link partner during next page exchange. - u[10:5] - reserved. transmit as 0 - u4 - 1000base-t half duplex. 1: half duplex 0: no half duplex - u3 - 1000base-t full duplex. 1: full duplex 0: no full duplex - u2 - 1000base-t port type bit. 1: multi-port device 0: single-port device register 9.10 (gbcr) table 32, page 37. u1 - 1000base-t master-slave manual configuration value. 1: master 0: slave this bit is ignored if bit 9.12=0 register 9.11 (gbcr) table 32, page 37. u0 - 1000base-t master-slave manual configuration enable. 1: manual configuration enable this bit is intended to be used for manual selection in master-slave mode, and is to be used in conjunction with bit 9.11 register 9.12 (gbcr) table 32, page 37.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 24 track id: jatr-3375-16 rev. 1. 6 bit name bit description register location page 2 (unformatted next page) u15 np next page. 1: indicates that next pages follow 0: indicates that no next pages follow - u14 ack acknowledge. 1: indicates that a device ha s successfully received its link partner?s link code word (lcw) - u13 mp message page. 1: indicates to its link partner that this is a message page, not an unformatted page - u12 ack2 acknowledge 2. 1: indicates to its link partner that the device has the ability to comply with the message - u11 t toggle. used by the nway arbitration function to ensure synchronization with its link partner during next page exchange. - u[10:0] - 1000base-t master-slave seed bit[10:0] master-slave seed value sb[10:0] 7.11.1. auto-negotiation priority resolution upon the start of auto-negotiation, to advertise its capabilities each station transmits a 16-bit packet called a link code word (lcw), within a burst of 17 to 33 fast link pulses (flp). a device capable of auto-negotiation transmits and receives the flps. the receiver must identify three identical lcws before the information is authenticated and used in the arb itration process. the devices decode the base lcw and select capabilities with the highest common denominator supported by both devices. to advertise 1000base-t capability, both link partners, sharing the same link medium, should engage in next page (1000base-t message page, unformatted page 1, and unformatted page 2) exchange. auto-negotiation ensures that the highest priority prot ocol will be selected as the link speed based on the following priorities advertised through the link code word (lcw) exchange. refer to ieee 802.3 clause 28 for detailed information. 1. 1000base-t full duplex (highest priority) 2. 1000base-t half duplex 3. 100base-tx full duplex 4. 100base-tx half duplex 5. 10base-t full duplex 6. 10base-t half duplex (lowest priority)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 25 track id: jatr-3375-16 rev. 1. 6 7.11.2. auto-negotiation master/slave resolution to establish a valid 1000base-t link, the master/slave mode of both link partners should be resolved through the auto-negotiation process: ? master priority ? multi-port > single-port ? manual > non-manual ? determination of master/slave configuration from lcw ? manual_master=u0*u1 ? manual_slave=u0*!u1 ? single-port device=!u0*!u2 ? multi-port device=!u0*u2 where: u0 is bit 0 of the unformatted page 1 u1 is bit 1 of the unformatted page 1 u2 is bit 2 of the unformatted page 1 ? where there are two stations with the same configuration, the one with higher master-slave seed sb[10:0] in the unformatted page 2 shall become master. ? master-slave configuration process resolution: ? successful: bit 10.15 master-slave configuration fault is set to logical 0, and bit 10.14 is set to logical 1 for master resolution, or set to logical 0 for slave resolution. ? unsuccessful: auto-negotiation restarts. ? fault detect: bit 10.15 is set to l ogical 1 to indicate that a configuration fault has been detected. auto-negotiation restarts automatically. this happens when both stations are set to manual master mode or manual slave mode, or after seven attempts to configure the master-slave relationship through the seed method has failed. 7.11.3. auto-negotiation pause/asymmetric pause resolution auto-negotiation is also used to determine the flow control capability between link partners. flow control is a mechanism that can force a busy transmitting link partner to stop transmitting in a full duplex environment by sending special mac control frames . in ieee 802.3u, a pause control frame had already been defined. however, in ieee 802.3ab, a new asy-pause control fram e was defined; if the mac can only generate pause frames but is not able to re spond to pause frames generated by the link partner, then it is called asymmetric pause. pause/asymmetric pause capability can be confi gured by setting the anar bits 10 and 11 (table 27, page 34). link partner pause capabilities can be de termined from anlpar bits 10 and 11 (table 28, page 35). a phy layer device such as the rtl8211e-v b(vl)/rtl8211eg-vb is not directly involved in pause resolution, but simply advertises and re ports pause capabilities during the auto-negotiation process. the mac is responsible for final paus e/asymmetric pause resolution after a link is established, and is responsible for correct flow control actions thereafter.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 26 track id: jatr-3375-16 rev. 1. 6 7.12. crossover detection and auto-correction ethernet needs a crossover mechanism between both link partners to cross the transmit signal to the receiver when the medium is twisted-pair cable. cr ossover detection & auto-correction configuration eliminates the need for crossover cables between devi ces, such as two computers connected to each other with a cat.5 ethernet cable. the ba sic concept is to assume the initial default setting is mdi mode, and then check the link status. if no link is established af ter a certain time, change to mdi crossover mode and repeat the process until a link is established. an 11-b it pseudo-random timer is applied to decide the mode change time interval. crossover detection & auto-correction is not a part of the auto-negotiation process, but it utilizes the process to exchange the mdi/mdi crossover c onfiguration. if the rtl 8211e-vb(vl)/rtl8211eg-vb is configured to only operate in 100base-tx or only in 10base-t mode, then auto-negotiation is disabled only if the crossover detection & auto-correction f unction is also disabled. if crossover detection & auto-correction are enabled, then auto-nego tiation is enabled and the rtl8211e-vb(vl)/ rtl8211eg-vb advertises only 100base-tx mode or 10base-t mode. if the speed of operation is configured manually and auto-negotiation is s till enabled because the crossover detection & auto-correction function is enabled, then the duplex advertised is as follows: 1. if config is set to half duplex, then only half duplex is advertised. 2. if config is set to full duplex, then both full and half duplex are advertised. if the user wishes to advertise only full duplex at a particular speed with the crossover detection & auto-correction function enabled, then auto-nego tiation should be enabled (register 0.12) with the appropriate advertising capabilities set in registers 4 or 9. the crossover detection & auto-correction function may be enabled/disabled by setting (register 16.6) manually. after initial configuration following a hardware reset, auto-negotiation can be enabled and disabled via register 0.12, speed via registers 0.13, 0.6, and duplex via register 0.8. the abilities that are advertised can be changed via registers 4 and 9. changes to regi sters 0.12, 0.13, 0.6, and 0.8 do not take effect unless at least one of the following events occurs: ? software reset (register 0.15) ? restart of auto-negotiation (register 0.9) ? transition from power-down to power-up (register 0.11) registers 4 and 9 are internally latched once each time auto-negotiation enters the ability detect state in the arbitration state machine (ieee 802.3). hence a write into register 4 or 9 has no effect once the rtl8211e-vb(vl)/rtl8211eg-vb begins to transmit fast link pulses. register 7 is treated in a similar manner as 4 and 9 during additional next page exchanges. once the rtl8211e-vb(vl)/rtl8211eg-vb completes auto-ne gotiation, it updates the various statuses in registers 1, 5, 6, and 10. the speed, duplex, page received, and auto-negotiation completed statuses are also available in registers 17 and 19.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 27 track id: jatr-3375-16 rev. 1. 6 7.13. led configuration the rtl8211e-vb(vl)/rtl8211eg-vb supports thr ee led pins, suitable for multiple types of applications that can directly drive the leds. th e output of these pins is determined by setting the corresponding bits in extension page44 register 28 and register 26. the functionality of the rtl8211e-vb(vl)/rtl8211eg-vb leds is shown in table 17. table 17. led default definitions pin description led0 blinking=transm itting or receiving led1 low=link up (any speed) high=link down (any speed) led2 low=link up (any speed) high=link down (any speed) blinking=transmitti ng or receiving note: when in eee mode, blinking dura tion is 400ms on and 2 seconds off. the rtl8211e-vb(vl)/rtl8211eg-vb led pins can be customized from extension page 44 register 28 and register 26. to ch ange the register page, see note (below) and table 18. there are 16 configuration types (see table 19, page 28). note: to switch to extension page44, set register 31 data=0x0007 (set to extension page). set register 30 data=0x002c (extension page44). after led setting, switch to phy`s page0 (register 31 data=0000). table 18. led register table link speed active (tx/rx) 10mbps 100mbps 1000mbps led0 reg28 bit0 reg28 bit1 reg28 bit2 reg26 bit4 led1 reg28 bit4 reg28 bit5 reg28 bit6 reg26 bit5 led2 reg28 bit8 reg28 bit9 reg28 bit10 reg26 bit6
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 28 track id: jatr-3375-16 rev. 1. 6 table 19. led configuration table pin link bit active (tx/rx) bit description 10 100 1000 0 0 0 0 n/a 0 0 0 1 active 0 0 1 0 link 1000 0 0 1 1 link 1000+active 0 1 0 0 link 100 0 1 0 1 link 100+active 0 1 1 0 link 100/1000 0 1 1 1 link 100/1000+active 1 0 0 0 link 10 1 0 0 1 link 10+active 1 0 1 0 link 10/1000 1 0 1 1 link 10/1000+active 1 1 0 0 link 10/100 1 1 0 1 link 10/100+active 1 1 1 0 link 10/100/1000 led 1 1 1 1 link 10/100/1000+active 7.14. polarity correction the rtl8211e-vb(vl)/rtl8211eg-vb automatically co rrects polarity errors on the receive pairs in 1000base-t and 10base-t modes. in 100base-tx mode polarity is irrelevant. in 1000base-t mode, receive polarity errors are automatically corrected based on the sequence of idle symbols. once the descrambler is locked, the polarity is also locked on all pairs. the polarity becomes unlocked only when the receiver loses lock. in 10base-t mode, polarity errors are corrected based on the detection of validly spaced link pulses. the detection begins during the mdi crossover detection phase and locks when the 10base-t link is up. the polarity becomes unlocked when the link is down.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 29 track id: jatr-3375-16 rev. 1. 6 7.15. power the rtl8211e-vb(vl)/rtl8211eg-vb implements a vo ltage regulator to generate operating power. the system vendor needs to supply a 3.3v, 1a steady power source. the rtl8211e-vb(vl)/ rtl8211eg-vb converts the 3.3v steady power source to 1.05v via a switching regulator. another possible implementation is to use an external re gulator to generate 1.0v. be sure that the regulator meets the required current rate (0.95v~1.09v). the rtl8211e-vb(vl)/rtl8211eg-vb implements an option for the rgmii/gmii power pins. the standard i/o voltage of the rgmii/gmii interface is 3.3v, with support for 2.5v to lower emi. the 2.5v power source for rgmii is from an external regulator. 7.16. phy reset (hardware reset) the rtl8211e-vb(vl)/rtl8211eg-vb has a phyrstb pin to reset the chip. for a complete phy reset, this pin must be asserted low for at least 10m s (tgap in figure 10) for the internal regulator. wait for a further 30ms (for internal circuits settling time) before accessing the phy register. all registers will return to default values after a hardware rese t. refer to the rtl8211xx-xx_power_sequence_app_note for more detailed information. tgap (10ms) 1 . 0v phyrstb wait 30ms before accessing the phy register figure 10. phy reset timing
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 30 track id: jatr-3375-16 rev. 1. 6 8. register descriptions 8.1. register mapping and definitions table 20. register mapping and definitions offset access name description 0 rw bmcr basic mode control register. 1 ro bmsr basic mode status register. 2 ro phyid1 phy identifier register 1. 3 ro phyid2 phy identifier register 2. 4 rw anar auto-negotiati on advertising register. 5 rw anlpar auto-negotiation link partner ability register. 6 rw aner auto-negotiation expansion register. 7 rw annptr auto-negotiation ne xt page transmit register. 8 rw annprr auto-negotiation ne xt page receive register. 9 rw gbcr 1000base-t control register. 10 ro gbsr 1000base-t status register. 11~12 ro rsvd reserved. 13 wo macr mmd access control register. 14 rw maadr mmd access address data register. 15 ro gbesr 1000base-t extended status register. 16 rw phycr phy specific control register. 17 ro physr phy specific status register. 18 rw iner interrupt enable register. 19 ro insr interrupt status register. 20~23 rw rsvd reserved. 24 ro rxerc receive error counter. 25~26 rw rsvd reserved. 27 ro ldpsr link down power saving register. 28 ro rsvd reserved. 29 rw rsvd reserved. 30 rw epagsr extension page select register. 31 rw pagsel page select register. note: to switch to extension page44, set register 31 data=0 x0007 (set to extension page). set register 30 data=0x002c (extension page44). after led setting, switch to the phy?s page0 (register 31 data=0000).
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 31 track id: jatr-3375-16 rev. 1. 6 8.2. mmd register mapping and definition table 21. mmd register mapping and definition device offset access name description 3 0 rw pc1r pcs control 1 register. 3 1 rw ps1r pcs status 1 register. 3 20 ro eeecr eee capability register. 3 22 rc eeewer eee wake error register. 7 60 rw eeear eee advertisement register. 7 61 ro eeelpar eee link pa rtner ability register. 8.3. extpage register mapping and definition table 22. extpage register mapping and definition extpage offset access name description 44 26 rw lacr led action control register. 44 28 rw lcr led control register. 45 24 rw accr auto-crossover control register. 8.4. register table 8.4.1. bmcr (basic mode control register, address 0x00) table 23. bmcr (basic mode control register, address 0x00) bit name rw default description 0.15 reset rw, sc 1 0 reset. 1: phy reset 0: normal operation register 0 (bmcr) and register 1 (bmsr) will return to default values after a software reset (set bit15 to 1). this action may change the internal phy state and the state of the physical link associated with the phy. 0.14 loopback rw 0 loopback mode. 1: enable pcs loopback mode 0: disable pcs loopback mode
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 32 track id: jatr-3375-16 rev. 1. 6 bit name rw default description 0.13 speed[0] rw 0 speed select bit 0. in forced mode, i.e., when auto-negotiation is disabled, bits 6 and 13 determine device speed selection. speed[1] speed[0] speed enabled 1 1 reserved 1 0 reserved 0 1 100mbps 0 0 10mbps 0.12 ane rw 1 auto-negotiation enable. 1: enable auto-negotiation 0: disable auto-negotiation 0.11 pwd rw 0 power down. 1: power down (only management in terface and logic are active; link is down) 0: normal operation 0.10 isolate rw 0 isolate. 1: rgmii/gmii interface is isolated ; the serial management interface (mdc, mdio) is still active. when this bit is asserted, the rtl8211e-vb(vl)/rtl8211eg-vb ignores txd[7:0], and txctl inputs, and presents a high impedance on txc, rxc, rxctl, rxd[7:0]. 0: normal operation 0.9 restart_an rw, sc 0 restart auto-negotiation. 1: restart auto-negotiation 0: normal operation 0.8 duplex rw 1 duplex mode. 1: full duplex operation 0: half duplex operation this bit is valid only in force mode, i.e., nway is disabled. 0.7 collision test rw 0 collision test. 1: collision test enabled 0: normal operation 0.6 speed[1] rw 1 speed select bit 1. refer to bit 0.13. 0.5:0 rsvd ro 000000 reserved. note 1: sc: self-cleared. note 2: the power-on duplex, speed, and ane values take on the values set by external pins an[1:0] on hardware reset only. a write to these registers has no effect unless any one of the following also occurs: software reset (0.15) is asserted, restart_an (0.9) is asserted, or pwd (0.11) transitions from power down to normal operation. note 3: when the rtl8211e-vb(vl)/rtl8211eg-vb is switched from power down to normal operation, a software reset and restart auto-negotiation is performed, even if bits rese t (0.15) and restart_an (0.9) are not set by the user. note 4: auto-negotiation is enabled when speed is set to 1000base-t. crossover detection & auto-correction takes precedence over auto-negotiation disabl e (0.12=0). if ane is disabled, sp eed and duplex capabilities are advertised by 0.13, 0.6, and 0.8. otherwise, register 4.8:5 and 9.9:8 take effect. note 5: auto-negotiation automatically restarts after hardware or software reset regardless of whether or not the restart bit (0.9) is set.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 33 track id: jatr-3375-16 rev. 1. 6 8.4.2. bmsr (basic mode status register, address 0x01) table 24. bmsr (basic mode status register, address 0x01) bit name rw default description 1.15 100base-t4 ro 0 100base-t4 capability. the rtl8211e-vb(vl)/rtl8211eg-vb does not support 100base-t4 mode. this bit should always be 0. 1.14 100base-tx (full) ro 1 100bas e-tx full duplex capability. 1: device is able to perform 100base-tx in full duplex mode 0: device is not able to perform 100base-tx in full duplex mode 1.13 100base-tx (half) ro 1 100base-tx half duplex capability. 1: device is able to perform 100base-tx in half duplex mode 0: device is not able to perform 100base-tx in half duplex mode 1.12 10base-t (full) ro 1 10base-t full duplex capability. 1: device is able to perform 10base-t in full duplex mode. 0: device is not able to perform 10base-t in full duplex mode. 1.11 10base-t (half) ro 1 10base-t half duplex capability. 1: device is able to perform 10base-t in half duplex mode 0: device is not able to perform 10base-t in half duplex mode 1.10 10base-t2 (full) ro 0 10base-t2 full duplex capability. the rtl8211e-vb(vl)/rtl8211eg-vb does not support 10base-t2 mode and this bit should always be 0. 1.9 10base-t2 (half) ro 0 10base-t2 half duplex capability. the rtl8211e-vb(vl)/rtl8211eg-vb does not support 10base-t2 mode. this bit should always be 0. 1.8 1000base-t extended status ro 1 1000base-t extended status register. 1: device supports extended status register 0x0f (15) 0: device does not support extended status register 0x0f this register is read-only and is always set to 1. 1.7 rsvd ro 0 reserved. 1.6 preamble suppression ro 1 preamble suppression capability (permanently on). the rtl8211e-vb(vl)/rtl8211eg-vb always accepts transactions with preamble suppressed. 1.5 auto-negotiation complete ro 0 auto-negotiation complete. 1: auto-negotiation process complete, and contents of registers 5, 6, 8, and 10 are valid 0: auto-negotiation process not complete 1.4 remote fault rc* 0 remote fault. 1: remote fault condition detected (cleared on read or by reset). indication or notification of remote fault from link partner 0: no remote fault condition detected 1.3 auto-negotiation ability ro 1 auto configured link. 1: device is able to perform auto-negotiation 0: device is not able to perform auto-negotiation
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 34 track id: jatr-3375-16 rev. 1. 6 bit name rw default description 1.2 link status ro 0 link status. 1: linked 0: not linked this register indicates whether the link was lost since the last read. for the current link status, either r ead this register twice or read register bit 17.10 link real time. 1.1 jabber detect rc 0 jabber detect. 1: jabber condition detected 0: no jabber occurred 1.0 extended capability ro 1 1: extended register capabilities, always 1 note: rc: read-cleared after read. 8.4.3. phyid1 (phy identifier register 1, address 0x02) table 25. phyid1 (phy identi fier register 1, address 0x02) bit name rw default description 2.15:0 oui_msb ro 0000000000011100 organizationally unique identifier bit 3:18. always 0000000000011100. note: realtek oui is 0x000732. 8.4.4. phyid2 (phy identifier register 2, address 0x03) table 26. phyid2 (phy identi fier register 2, address 0x03) bit name rw default description 3.15:10 oui_lsb ro 110010 organizationally unique identifier bit 19:24. always 110010. 3.9:4 model number ro 010001 manufacture?s model number 3.3:0 revision number ro 0101 revision number 8.4.5. anar (auto-negotiation advertising register, address 0x04) table 27. anar (auto-negotiation advertising register, address 0x04) bit name rw default description 4.15 nextpage rw 0 1: additiona l next pages exchange desired 0: no additional next pages exchange desired 4.14 rsvd ro 0 reserved. 4.13 remote fault rw 0 1: set remote fault bit 0: no remote fault detected 4.12 rsvd ro 0 reserved. 4.11 asymmetric pause rw 0 1: advertise support of asymmetric pause 0: no support of asymmetric pause
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 35 track id: jatr-3375-16 rev. 1. 6 bit name rw default description 4.10 pause rw 1 1: advertise support of pause frames 0: no support of pause frames 4.9 100base-t4 ro 0 1: 100base-t4 support 0: 100base-t4 not supported 4.8 100base-tx (full) rw 1 1: advertise support of 100base-tx full-duplex mode 0: not advertised 4.7 100base-tx (half) rw 1 1: advertise support of 100base-tx half-duplex mode 0: not advertised 4.6 10base-t (full) rw 1 1: advertise support of 10base-tx full-duplex mode 0: not advertised 4.5 10base-t (half) rw 1 1: advertise support of 10base-tx half-duplex mode 0: not advertised 4.4:0 selector field ro 00001 indicates the rtl8211e-vb(vl)/rtl8211eg-vb supports ieee 802.3 note 1: the setting of register 4 has no effect unless nway is restarted or the link goes down. note 2: if 1000base-t is advertised, then the required next page s are automatically transmitted. register 4.15 should be set to 0 if no additional next pages are needed. 8.4.6. anlpar (auto-negotiation link partner ability register, address 0x05) table 28. anlpar (auto-negotiation link partner ability register, address 0x05) bit name rw default description 5.15 next page ro 0 next page indication. received code word bit 15. 5.14 ack ro 0 acknowledge. received code word bit 14. 5.13 remote fault ro 0 remote fault indicated by link partner. received code word bit 13. 5.12 rsvd ro 0 reserved. 5.11:5 technology ability field ro 00000000 received code word bit 12:5. 5.4:0 selector field ro 00000 r eceived code word bit 4:0. note: register 5 is not valid until the auto-negotiation complete bit 1.5 indicates completed.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 36 track id: jatr-3375-16 rev. 1. 6 8.4.7. aner (auto-negotiation expansion register, address 0x06) table 29. aner (auto-negotiation expansion register, address 0x06) bit name rw default description 6.15:5 rsvd ro 0x000 reserved. 6.4 parallel detection fault rc 0 1: a fault has been detected via the parallel detection function 0: a fault has not been detected via the parallel detection function 6.3 link partner next pageable ro 0 1: link partner supports next page exchange 0: link partner does not support next page exchange 6.2 local next pageable ro 1 1: local device is able to send next page always 1. 6.1 page received rc 0 1: a new pa ge (new lcw) has been received 0: a new page has not been received 6.0 link partner auto-negotiation capable ro 0 1: link partner supports auto-negotiation 0: link partner does not support auto-negotiation note: register 6 is not valid until the auto-negotiation complete bit 1.5 indicates completed. 8.4.8. annptr (auto-negotiation next page transmit register, address 0x07) table 30. annptr (auto-negotiation next page transmit register, address 0x07) bit name rw default description 7.15 next page rw 0 next page indication. 0: no more next pages to send 1: more next pages to send transmit code word bit 15. 7.14 rsvd ro 0 transmit code word bit 14. 7.13 message page rw 1 message page. 0: unformatted page 1: message page transmit code word bit 13. 7.12 acknowledge 2 rw 0 acknowledge2. 0: local device has no ability to comply with the message received 1: local device has the ability to comply with the message received transmit code word bit 12. 7.11 toggle ro 0 toggle bit. transmit code word bit 11. 7.10:0 message/unformatted field rw 0x001 content of message/unformatted page. transmit code word bit 10:0.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 37 track id: jatr-3375-16 rev. 1. 6 8.4.9. annprr (auto-negotiation next page receive register, address 0x08) table 31. annprr (auto-negotiation next page receive register, address 0x08) bit name rw default description 8.15 next page ro 0 receive d link code word bit 15. 8.14 acknowledge ro 0 receive d link code word bit 14. 8.13 message page ro 0 recei ved link code word bit 13. 8.12 acknowledge 2 ro 0 receive d link code word bit 12. 8.11 toggle ro 0 received link code word bit 11. 8.10:0 message/unformatted field ro 0x00 received link code word bit 10:0. note: register 8 is not valid until the auto-negotiation complete bit 1.5 indicates completed. 8.4.10. gbcr (1000base-t control register, address 0x09) table 32. gbcr (1000base-t control register, address 0x09) bit name rw default description 9.15:13 test mode rw 0 test mode select. 000: normal mode 001: test mode 1 ? transmit jitter test 010: test mode 2 ? transmit jitter test (master mode) 011: test mode 3 ? transmit jitter test (slave mode) 100: test mode 4 ? transmit distortion test 101, 110, 111: reserved 9.12 master/slave manual configuration enable rw 0 enable manual master/slave configuration. 1: manual master/slave configuration 0: automatic master/slave 9.11 master/slave configuration value rw 0 advertise master/slave configuration value. 1: manual configure as master 0: manual configure as slave 9.10 port type rw 0 advertise device type preference. 1: prefer multi-port device (master) 0: prefer single port device (slave) 9.9 1000base-t full duplex rw 1 adver tise 1000base-t full-duplex capability. 1: advertise 0: do not advertise 9.8 rsvd rw 0 reserved. 9.7:0 rsvd ro 0 reserved. note 1: values set in register 9.12:9 have no effect unless auto-negotiation is restarted (reg0.9) or the link goes down. note 2: bits 9.11 and 9.10 are ignored when bit 9.12=0.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 38 track id: jatr-3375-16 rev. 1. 6 8.4.11. gbsr (1000base-t status register, address 0x0a) table 33. gbsr (1000base-t st atus register, address 0x0a) bit name rw default description 10.15 master/slave configuration fault ro, rc 0 master/slave manual configuration fault detected. 1: master/slave configuration fault detected 0: no master/slave configuration fault detected 10.14 master/slave configuration resolution ro 0 master/slave configuration result. 1: local phy configuration resolved to master 0: local phy configuration resolved to slave 10.13 local receiver status ro 0 local receiver status. 1: local receiver ok 0: local receiver not ok 10.12 remote receiver status ro 0 remote receiver status. 1: remote receiver ok 0: remote receiver not ok 10.11 link partner 1000base-t full duplex capability ro 0 link partner 1000base-t full duplex capability. 1: link partner is capable of 1000base-t full duplex 0: link partner is not capable of 1000base-t full duplex 10.10 link partner 1000base-t half duplex capability ro 0 link partner 1000base-t half duplex capability. 1: link partner is capable of 1000base-t half duplex 0: link partner is not capable of 1000base-t half duplex 10.9:8 rsvd ro 00 reserved. 10.7:0 idle error count ro, rc 0x00 msb of idle error counter. the counter stops automatically when it reaches 0xff. note 1: values set in register 10.11:10 are not valid until register 6.1 is set to 1. note 2: register 10 is not valid until the auto-negotiation complete bit 1.5 indicates completed. 8.4.12. macr (mmd access control register, address 0x0d) table 34. macr (mmd access control register, address 0x0d) bit name rw default description 13.15:14 function wo 0 00: address 01: data with no post increment 10: data with post increment on reads and writes 11: data with post increment on writes only 13.13:5 rsvd ro 000000000 reserved. 13.4:0 devad wo 0 device address. note 1: this register is used in conjunction with the maadr (register 14) to provide access to the mmd address space. note 2: if the maadr accesses for address (function=00), then it is directed to the address register within the mmd associated with the value in the devad field. note 3: if the maadr accesses for data (function 00), both the devad field and mmd?s address register direct the maadr data accesses to the appropriate registers within the mmd.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 39 track id: jatr-3375-16 rev. 1. 6 8.4.13. maadr (mmd access address data register, address 0x0e) table 35. maadr (mmd access address data register, address 0x0e) bit name rw default description 14.15:0 address data rw 0x0000 13.15:14 = 00 ? mmd devad?s address register 13.15:14 = 01, 10, or 11 ? mmd devad?s data register as i ndicated by the contents of its address register note: this register is used in conjunction with the macr (register 13; table 34) to provide access to the mmd address space. 8.4.14. gbesr (1000base-t extended status register, address 0x0f) table 36. gbesr (1000base-t extende d status register, address 0x0f) bit name rw default description 15.15 1000base-x fd ro 0 0: not 1000base-x full duplex capable 15.14 1000base-x hd ro 0 0: not 1000base-x half duplex capable 15.13 1000base-t fd ro 1 1: 1000base-t full duplex capable 15.12 1000base-t hd ro 1 1: 1000base-t half duplex capable 15.11:0 rsvd ro 0x000 reserved. 8.4.15. phycr (phy specific control register, address 0x10) table 37. phycr (phy specific control register, address 0x10) bit name rw default description 16.15 disable rxc rw 0 disable rxc clock output. 16.14:12 select fpr fail rw 000 se lect signal for ?lprfail? (10m link pulse receive status). 16.11 assert crs on transmit rw 1 (gmii) 0 (rgmii) 1: assert crs on transmit 0: never assert crs on transmit 16.10 force link good rw 0 1: force link good 0: normal operation 16.9:8 rsvd rw 01 reserved. 16.7 rsvd rw 0 reserved. 16.6 enable crossover rw 1 1: enable auto-crossover mechanism after setting mdi/mdix, perfo rm phy reset (register0, bit[15]=1) 16.5 mdi mode rw 1 used to determine mdi/mdix mode when auto-crossover is disabled. note: method 1 (set reg16.6=0 to disable auto crossover) 0: mdi mode 1: mdix mode method 2 (set extpage45_24.5=1 to disable auto-crossover) 0: mdix mode 1: mdi mode
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 40 track id: jatr-3375-16 rev. 1. 6 bit name rw default description 16.4 disable clk125 rw 0 1: clk125 remains at logic low 0: clk125 toggling enabled 16.3:1 rsvd rw 111 reserved. 16.0 disable jabber rw 0 1: disable ja bber function 0: enable jabber function note 1: there are two methods to disable auto-crossover and force mdi or mdix mode. method 1: step 1: set enable crossover reg16 bit[6]=0 (disables auto-crossover) and set mdi reg16 bit[5]=1 (mdix) or 0 (mdi). step 2: set phy reset reg0 bit[15]=1. method 2: set disable crossover extpage45 reg24, bit[5]=1 (disables auto-crossover) and set mdi reg16, bit[5]=1 (mdi) or 0 (mdix). note 2: to write extpage 45_reg.24 bit[5]=1: a. write reg31, data=0x0007 (page 7). b. write reg30, data=0x002d (extension page 45). c. write reg24, bit[5]=1. 8.4.16. physr (phy specific status register, address 0x11) table 38. physr (phy specific status register, address 0x11) bit name rw default description 17.15:14 speed ro 01 link speed. 11: reserved 10: 1000mbps 01: 100mbps 00: 10mbps 17.13 duplex ro 0 full/half duplex mode. 1: full duplex 0: half duplex 17.12 page received rc 0 new page received. 1: page received 0: page not received 17.11 speed and duplex resolved ro 0 speed and duplex mode resolved. 1: resolved 0: not resolved 17.10 link (real time) ro 0 real time link status. 1: link ok 0: link not ok 17.9:7 rsvd ro 000 reserved. 17.6 mdi crossover status ro 0 mdi/mdi crossover status. 1: mdi crossover 0: mdi 17.5:2 rsvd rw 0000 reserved. 17.1 pre_linkok ro 0 reflect s local receiver is ok. 0: receiver is not ok 1: receiver is ok 17.0 jabber (real time) ro 0 real time jabber indication. 1: jabber indication 0: no jabber indication
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 41 track id: jatr-3375-16 rev. 1. 6 8.4.17. iner (interrupt enable register, address 0x12) table 39. iner (interrupt enable register, address 0x12) bit name rw default description 18.15 auto-negotiation error interrupt rw 1 1: interrupt enable 0: interrupt disable setting this bit to 0 only masks an auto-negotiation error interrupt event in the intb pin. reg19 bit15 (section 8.4.18, page 42) always reflects the auto-negotiation error interrupt behavior. 18.14:13 rsvd rw 00 reserved. 18.12 page received interrupt rw 1 1: interrupt enab le 0: interrupt disable setting this bit to 0 only masks a page received interrupt event in the intb pin. reg19 bit12 (section 8.4.18, page 42) always reflects the page receive d interrupt behavior. 18.11 auto-negotiation completed interrupt rw 1 1: interrupt enable 0: interrupt disable setting this bit to 0 only masks an auto-negotiation completed interrupt event in the intb pin. reg19 bit11 (section 8.4.18, page 42) always reflects the auto-negotiation completed interrupt behavior. 18.10 link status change interrupt rw 1 1: interrupt enable 0: interrupt disable setting this bit to 0 only masks a link status change interrupt event in the intb pin. reg19 bit10 (section 8.4.18, page 42) always reflects the link change interrupt behavior. 18.9 symbol error interrupt rw 1 1: interrupt enable 0: interrupt disable setting this bit to 0 only masks a symbol error interrupt event in the intb pin. reg19 bit9 (section 8.4.18, page 42) always reflects the symbol error interrupt behavior. 18.8 false carrier interrupt rw 1 1: interrupt enable 0: interrupt disable setting this bit to 0 only masks a false carrier interrupt event in the intb pin. reg19 bit8 (section 8.4.18, page 42) always reflects the false carrier interrupt behavior. 18.7:1 rsvd rw 0000000 reserved. 18.0 jabber interrupt rw 1 1: interrupt enable 0: interrupt disable setting this bit to 0 only masks a jabber interrupt event in the intb pin. reg19 bit0 (section 8.4.18, page 42) always reflects the jabber interrupt behavior.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 42 track id: jatr-3375-16 rev. 1. 6 8.4.18. insr (interrupt status register, address 0x13) table 40. insr (interrupt status register, address 0x13) bit name rw default description 19.15 auto-negotiation error rc 0 1: auto-negotiation error 0: no auto-negotiation error 19.14:13 rsvd rc 00 reserved. 19.12 page received rc 0 1: pa ge (a new lcw) received 0: page not received 19.11 auto-negotiation completed rc 0 1: auto-negotiation completed 0: auto-negotiation not completed 19.10 link status change rc 0 1: link status changed 0: link status not changed 19.9 symbol error rc 0 1: symbol error detected 0: no symbol error detected 19.8 false carrier rc 0 1: false carri er 0: no false carrier detected 19.7:1 rsvd - 0000000 reserved. 19.0 jabber rc 0 1: jabber detected 0: no jabber detected 8.4.19. rxerc (receive error counter, address 0x18) table 41. rxerc (receive error counter, address 0x18) bit name rw default description 24.15:0 receive erro r count rc 0x0000 recei ve error count. note: the rxerc register is read-cleared after a read. 8.4.20. ldpsr (link down power saving register, address 0x1b) table 42. ldpsr (link down power saving register, address 0x1b) bit name rw default description 27.15:1 rsvd ro 0 reserved. 27.0 power save mode ro 0 link down power saving mode. 1: reflects local device enters link down power saving mode, i.e., cable not plugged in (will be reflected after 3 sec) 0: with cable plugged in (will be reflected 21ms after plugging in) 8.4.21. epagsr (extension page select register, address 0x1e) table 43. epagsr (extension page select register, address 0x1e) bit name rw default description 30.15:8 rsvd rw 0 reserved. 30.7:0 extpagesel rw 0x00 extension page select (in hex). note: this register is used in conjunction with the pagsel (register 31) to provide access to the extension page space. values in this register are valid only if 31.2:0 (pagesel)=111.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 43 track id: jatr-3375-16 rev. 1. 6 8.4.22. pagsel (page select register, address 0x1f) table 44. pagsel (page select register, address 0x1f) bit name rw default description 31.15:3 rsvd rw 0 reserved. 31.2:0 pagesel rw 000 page select signal. 000: page 0 (default page) 001: page 1 010: page 2 011: page 3 100: page 4 101: page 5 110: page 6 111: extension page 8.4.23. pc1r (pcs control 1 register, mmd device 3, address 0x00) table 45. pc1r (pcs control 1 register, mmd device 3, address 0x00) bit name rw default description 3.0.15:11 rsvd rw 0 reserved. 3.0.10 clock stop enable rw 0 1: phy stops rxc in lpi 0: rxc not stoppable 3.0.9:0 rsvd rw 0 reserved. 8.4.24. ps1r (pcs status1 register, mmd device 3, address 0x01) table 46. ps1r (pcs status 1 register, mmd device 3, address 0x01) bit name rw default description 3.1.15:12 rsvd ro 0 reserved. 3.1.11 tx lpi received ro, lh 0 1: tx pcs has received lpi 0: lpi not received 3.1.10 rx lpi received ro,lh 0 1: rx pcs has received lpi 0: lpi not received 3.19 tx lpi indication ro 0 1: tx pcs is currently receiving lpi 0: tx pcs is not cu rrently receiving lpi 3.1.8 rx lpi indication ro 0 1: rx pcs is currently receiving lpi 0: rx pcs is not cu rrently receiving lpi 3.1.7 rsvd ro 0 reserved. 3.1.6 clock stop capable ro 1 1: mac stops txc in lpi 0: txc not stoppable 3.1.5:0 rsvd ro 0 reserved.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 44 track id: jatr-3375-16 rev. 1. 6 8.4.25. eeecr (eee capability register, mmd device 3, address 0x14) table 47. eeecr (eee capability register, mmd device 3, address 0x14) bit name rw default description 3.20.15:3 rsvd ro 0 reserved. 3.20.2 1000base-t eee ro 1 1: eee is supported for 1000base-t eee 0: eee is not supported for 1000base-t eee 3.20.1 100base-tx eee ro 1 1: eee is supported for 100base-tx eee 0: eee is not supported for 100base-tx eee 3.20.0 rsvd ro 0 reserved. 8.4.26. eeewer (eee wake error register, mmd device 3, address 0x16) table 48. eeewer (eee wake error re gister, mmd device 3, address 0x16) bit name rw default description 3.22.15:0 eee wake error counter rc 0 used by phy types that support eee to count wake time faults where the phy fails to complete its normal wake sequence within the time required for the specific phy type . 8.4.27. eeear (eee advertisement register, mmd device 7, address 0x3c) table 49. eeear (eee advertisement register, mmd device 7, address 0x3c) bit name rw default description 7.60.15:3 rsvd rw 0 reserved. 7.60.2 1000base-t eee rw 1 advertise 1000base-t eee capability. 1: advertise 0: do not advertise 7.60.1 100base-tx eee rw 1 advertise 100base-tx eee capability. 1: advertise 0: do not advertise 7.60.0 rsvd rw 0 reserved. 8.4.28. eeelpar (eee link partner ability register, mmd device 7, address 0x3d) table 50. eeelpar (eee link partner ability register, mmd device 7, address 0x3d) bit name rw default description 7.61.15:3 rsvd ro 0 reserved. 7.61.2 lp 1000base-t eee ro 0 1: link partner is capable of 1000base-t eee 0: link partner is not capable of 1000base-t eee 7.61.1 lp 100base-tx eee ro 0 1: link partner is capable of 100base-tx eee 0: link partner is not capable of 100base-tx eee 7.61.0 rsvd ro 0 reserved.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 45 track id: jatr-3375-16 rev. 1. 6 8.4.29. lacr (led action control register, extpage 0x2c, address 0x1a) table 51. lacr (led action control register, extpage 0x2c, address 0x1a) bit name rw default description 15:7 rsvd ro 0 reserved. 6:4 ledactctrl rw 101 led blinking mode setting. 1: blinking mode 0: steady mode 3:0 rsvd ro 0 reserved. note: this register is used in conjunction with the led control register (extpage 44, register 28). 8.4.30. lcr (led control register, extpage 0x2c, address 0x1c) table 52. lcr (led control register, extpage 0x2c, address 0x1c) bit name rw default description 15:11 rsvd ro 0 reserved. 10:8 led2 control ro 111 led2 control bits. 7 rsvd ro 0 reserved. 6:4 led1 control ro 111 led1 control bits. 3 rsvd ro 0 reserved. 2:0 led0 control ro 000 led0 control bits. note: this register is used in conjunction with the led action control register (extpage 44, register 26). 8.4.31. accr (auto-crossover control register, extpage 0x2d, address 0x18) table 53. accr (auto-crossover control register, extpage 0x2d, address 0x18) bit name rw default description 15:6 rsvd ro 0 reserved. 5 disable crossover rw 0 1: disable auto-c rossover and determine mdi/mdix mode via bit 16.5. 4:0 rsvd ro 0 reserved.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 46 track id: jatr-3375-16 rev. 1. 6 9. switching regulator the rtl8211e-vb(vl)/rtl8211eg-vb incorporates a st ate-of-the-art switching regulator that requires a well-designed pcb layout in order to achieve good pow er efficiency and lower the output voltage ripple and input overshoot. the switching re gulator 1.05v output pin (reg_out) should be connected only to dvdd10 and avdd10 (do not provide this power source to other devices). 9.1. pcb layout ? the input 3.3v power trace connected to vddreg must be wider than 40mils ? the bulk de-coupling capacitors (cin1 and cin2) mu st be placed within 200mils (0.5cm) of vddreg to prevent input voltage overshoot ? the output power trace out of reg_out must be wider than 60mils ? lx (2.2h/4.7h) must be kept within 200mils (0.5cm) of reg_out ? cout1 and cout2 must be kept within 200mils (0.5cm) of lx to ensure stable output power and better power efficiency ? for switching regulator stability, the capacitor cout1 and cout2 must be a ceramic (x5r) capacitor. cin1 and cin2 are recommended to be ceramic capacitors ? place lx and cin1 on the same layer as the rtl8211e-vb(vl)/rtl8211eg-vb. do not use vias on vddreg and reg_out traces note: violation of the above rules will damage the ic. figure 11. switching regulator
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 47 track id: jatr-3375-16 rev. 1. 6 9.2. inductor and capacitor parts list table 54. inductor and capacitor parts list inductor type inductance max idc (ma) variation output ripple (mv) glk2510p-2r2m 2.2h 1000 20% (see figure 15, figure 16) glk2510p-4r7m 4.7h 750 20% (see figure 17, figure 18) gtsd32p-2r2m 2.2h 1500 20% (see figure 19) note 1: the esr is equivalent to rd c or dcr. lower esr inductor values will promote a higher-efficiency switching regulator. note 2: the power inductor used by the switching regulator must be able to withstand 600ma of current. note 3: typically, if the power inductor?s esr at 1mhz is below 0.8 ? , the switching regulator efficiency will be above 75%. however the actual switching re gulator efficiency should be measured accord ing to the method desc ribed in section 9.4 efficiency measurement, page 54. note 4: if the inductor does not meet this requirement, it may damage the switching regulator. refer to the rtl8211e_eg inductor approved vendor list (avl) for details. capacitor type capacitance esr at 1mhz (m ? ) output ripple (mv) 4.7f 0805 x5r tdk 4.838 40.28 (see figure 15, figure 17) 10f 0603 x5r yageo 11.956 58.29 (see figure 16, figure 18) note: capacitors (cin1 & cin2) must be cer amic due to their low esr value. lo wer esr values will yield lower output voltage ripple.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 48 track id: jatr-3375-16 rev. 1. 6 9.3. measurement criteria in order for the switching regulator to operate prope rly, the input and output voltage measurement criteria must be met. from the input side, the voltage ove rshoot cannot exceed 4v; otherwise the chip may be damaged. note that the voltage signal must be measur ed directly at the vddreg pin, not at the capacitor. in order to reduce the input voltage overshoot, the ci n1 and cin2 must be placed close to the vddreg pin. the following figures show what a good input voltage and a bad one look like. figure 12. input voltage overshoot <4v (good) figure 13. input voltage overshoot >4v (bad)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 49 track id: jatr-3375-16 rev. 1. 6 from the output side measured at the reg_ out pin, the voltage ripple must be within 100mv peak-to-peak. choosing different types and va lues of input and output capacitor (cin1, cin2; cout1, cout2) and power inductor (lx) will seriously affect the efficiency and output voltage ripple of switching regulators. the following figures show the effects of different types of capacitors on the switching regulator?s output voltage. the blue square wave signal (top row) is measured at the output of the reg_out pin before the power inductor (lx). the yellow signal (second row) is measured after the power inductor (lx), and shows there is a voltage ripple. the green signal (lower row) is the current. data in the following figures was measured at gigabit speed. figure 14. ceramic 10f 0603 (x5r) (good) figure 15. l=glk2510p-2r2m, c=cerami c 4.7f 0805 x5r tdk (ripple 12.4mv)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 50 track id: jatr-3375-16 rev. 1. 6 figure 16. l=glk2510p-2r2m, c=cerami c 10f 0603 x5r yageo (ripple 13.2mv) figure 17. l=glk2510p-4r7m, c=cerami c 4.7f 0805 x5r tdk (ripple 12mv)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 51 track id: jatr-3375-16 rev. 1. 6 figure 18. l=glk2510p-4r7m, c=cerami c 10f 0603 x5r yageo (ripple 11.2mv) figure 19. l=gtsd32p-2r2m, c=cerami c 4.7f 0805 x5r tdk (ripple 9.2mv)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 52 track id: jatr-3375-16 rev. 1. 6 figure 20. ceramic 10f (y5v) (bad) a ceramic 10f (x5r) will have a lower voltage rippl e compared to an electrolytic 100f. the key to choosing a proper output capacitor is to choose the lowest esr to reduce the output voltage ripple. choosing a ceramic 10f (y5v) in this case will cause malfunction of the switching regulator. placing several electrolytic capacitors in parallel will help lower the output voltage ripple. figure 21. electrolytic 100f (ripple too high)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 53 track id: jatr-3375-16 rev. 1. 6 the following figures show how different inductors affect the reg_out output waveform. the typical waveform should look like figure 22, which has a square waveform with a dip at the falling edge and the rising edge. if the inductor is not carefully chos en, the waveform may look like figure 23, where the waveform looks like a distorted square. this will cau se insufficient current supply and will undermine the stability of the system at gigabit speed. data in the following figures was measured at gigabit speed figure 22. gtsd32p-2r2m (good) figure 23. 1h bead (bad)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 54 track id: jatr-3375-16 rev. 1. 6 9.4. efficiency measurement the efficiency of the switching regulator is designed to be above 75% in gigabit traffic mode. it is very important to choose a suitable inductor before gerber certification, as the inductor esr value will affect the efficiency of the switching regulator. an inductor with a lower esr value will result in a higher-efficiency switching regulator. the efficiency of the switching regulator is easily measured using the following method. figure 24 shows two checkpoints, checkpoint a (c p_a) and checkpoint b (cp_b). the switching regulator input current (icpa) should be measured at cp_a, and the switching regulator output current (icpb) should be measured at cp_b. to determine efficiency, apply the following formula: efficiency = vcpb*icpb / vcpa*icpa where vcpb is 1.05v; vcpa is 3.3v. the measurements should be performed in gigabit traffic mode. for example: the inductor used in the evaluation board is a gotrend gtsd32-4r7m: ? the esr value @ 1mhz is approximately 0.712ohm ? the measured icpa is 101ma at cp_a ? the measured icpb is 263ma at cp_b these values are measured in gigabit traffic mode , so the efficiency of the gotrend gtsd32-4r7m can be calculated as follows: efficiency = (1.05v*263ma) / (3.3v*101ma) = 0.823 = 82.3%. we strongly recommend that when choosing an inducto r for the switching regulator, the efficiency should be measured, and that the inductor should yield an effi ciency rating higher than 75%. if the efficiency does not meet this requirement, there may be risk to the switching regulator reliability in the long run. figure 24. switching regulator efficiency measurement checkpoint cp_b cp_a
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 55 track id: jatr-3375-16 rev. 1. 6 9.5. power sequence figure 25. power sequence table 55. power sequence parameter symbol description min typical max units rt1 3.3v rise time 1 - 100 ms rt1 2.5/1.8/1.5v rgmii rise time - - 100 ms rt2 3.3v off time 100 - - ms rt3 core logic ready time 20 - - ms note 1: the rtl8211e-vb(vl)/rtl8211eg-vb does not support fast 3.3v rising. the 3.3v rise time must be controlled over 1ms. if the rise time is too short, it will induce a peak voltage in vddreg which may cause permanent damage to the switching regulator. note 2: if there is any action that involves consecutive on/off toggling of the switching-regulator source (3.3v), the design must make sure the off state of both the switching-regulator source (3.3v) and output (1.05v) reach 0v, and the time period between the consecutive on/off toggling action must be longer than 100ms. note 3: when using an external oscillator or clock source, on stopping the clock source the rtl8211e-vb(vl)/rtl8211eg-vb must also be powered off. note 4: 2.5v (or 1.8/1.5v) rgmii power should be risen simult aneously or slightly earlier than 3.3v power. rising 2.5v (or 1.8/1.5v) power later than 3.3v power may lead to errors.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 56 track id: jatr-3375-16 rev. 1. 6 10. characteristics 10.1. absolute maximum ratings warning: absolute maximum ratings are limits beyond which permanent damage may be caused to the device, or device reliability will be affected. all vo ltages are specified reference to gnd unless otherwise specified. table 56. absolute maximum ratings symbol description minimum maximum unit vdd33, avdd33 supply voltage 3.3v -0.4 3.7 v avdd10, dvdd10 supply voltage 1.05v -0.1 1.26 v 2.5v rgmii/gmii supply voltage 2.5v -0.2 2.8 v 1.8v rgmii supply voltage 1.8v -0.2 2.3 v 1.5v rgmii supply voltage 1.5v -0.2 2.0 v dcinput input voltage -0.5 corresponding supply voltage + 0.5 v dcoutput output voltage -0.3 corresponding supply voltage + 0.5 v na storage temperature -55 +125 c note: refer to the most updated schematic circuit for correct configuration. 10.2. recommended operating conditions table 57. recommended operating conditions description pins minimum typical maximum unit dvdd33, avdd33 2.97 3.3 3.63 v avdd10, dvdd10 0.95 1.05 1.09 v 2.5v rgmii/gmii 2.4 2.5 2.62 v 1.8v rgmii 1.5 1.8 2.2 v supply voltage vdd 1.5v rgmii 1.43 1.5 1.9 v ambient operating temperature t a - 0 - 70 c maximum junction temperature - - - 125 c
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 57 track id: jatr-3375-16 rev. 1. 6 10.3. crystal requirements table 58. crystal requirements symbol description/condition minimum typical maximum unit f ref parallel resonant crystal reference frequency, fundamental mode, at-cut type. - 25 - mhz f ref stability parallel resonant crystal frequency stability, fundamental mode, at-cut type. ta=0 c~70 c. -30 - +30 ppm f ref tolerance parallel resonant crystal frequency tolerance, fundamental mode, at-cut type. ta=25 c. -50 - +50 ppm f ref duty cycle reference clock input duty cycle. 40 - 60 % esr equivalent series resistance. - - 30 ? dl drive level. - - 0.5 mw jitter broadband peak-to-peak jitter1, 2 - - 200 ps note 1: 25khz to 25mhz rms < 3ps. note 2: broadband rms < 9ps. 10.4. oscillator/external clock requirements table 59. oscillator/external clock requirements parameter condition minimum typical maximum unit frequency - - 25/50 - mhz frequency stability ta = 0c~70c -30 - 30 ppm frequency tolerance ta = 25c -50 - 50 ppm duty cycle - 40 - 60 % broadband peak-to-peak jitter 1, 2 - - - 200 ps vpeak-to-peak - 3.15 3.3 3.45 v rise time (10%~90%) - - - 10 ns fall time (10%~90%) - - - 10 ns operating temperature range - 0 - 70 c note 1: 25khz to 25mhz rms < 3ps. note 2: broadband rms < 9ps.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 58 track id: jatr-3375-16 rev. 1. 6 10.5. dc characteristics table 60. dc characteristics symbol parameter conditions minimum typical maximum units vdd33, avdd33 3.3v supply voltage - 2.97 3.3 3.63 v 1. mdio (table 5) 2. rgmii/gmii i/o (table 3/table 4) 2.5v rgmii/gmii supply voltage - 2.37 2.5 2.62 v 1. mdio (table 5) 2. rgmii i/o (table 3) 1.5v rgmii supply voltage - 1.43v 1.5v 1.9v v 1. mdio (table 5) 2. rgmii i/o (table 3) 1.8v rgmii supply voltage - 1.5v 1.8v 2.2v v dvdd10, avdd10 1.05v supply voltage - 0.95 1.05 1.09 v voh (3.3v) minimum high level output voltage - 0.9*vdd33 - vdd33 v voh (2.5v) minimum high level output voltage - 0.9*vdd25 - vdd25 v voh (1.8v) minimum high level output voltage - 0.9*vdd18 - vdd18 v voh (1.5v) minimum high level output voltage - 0.9*vdd15 - vdd15 v vol (3.3v) maximum low level output voltage - 0 - 0.1*vdd33 v vol (2.5v) maximum low level output voltage - 0 - 0.1*vdd25 v vol (1.8v) maximum low level output voltage - 0 - 0.1*vdd18 v vol (1.5v) maximum low level output voltage - 0 - 0.1*vdd15 v vih (3.3v) minimum high level input voltage - 1.8 - - v vil (3.3v) maximum low level input voltage - - - 0.9 v vih (2.5v) minimum high level input voltage - 1.7 - - v vil (2.5v) maximum low level input voltage - - - 0.7 v vih (1.8v) minimum high level input voltage - 1.2 - - v vil (1.8v) maximum low level input voltage - - - 0.5 v vih (1.5v) minimum high level input voltage - 1.0 - - v vil (1.5v) maximum low level input voltage - - - 0.3 v iin input current vin=vdd33 or gnd 0 - 0.5 a note: pins not mentioned above remain at 3.3v.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 59 track id: jatr-3375-16 rev. 1. 6 10.6. ac characteristics 10.6.1. mdc/mdio timing figure 26. mdc/mdio setup, hold time, and va lid from mdc rising edge time definitions mdc/mdio timing ? management port figure 27. mdc/mdio management timing parameters table 61. mdc/mdio management timing parameters symbol description minimum maximum unit t 1 mdc high pulse width 160 - ns t 2 mdc low pulse width 160 - ns t 3 mdc period 400 - ns t 4 mdio setup to mdc rising edge 10 - ns t 5 mdio hold time from mdc rising edge 10 - ns t 6 mdio valid from mdc rising edge 0 300 ns
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 60 track id: jatr-3375-16 rev. 1. 6 10.6.2. mii transmission cycle timing (rtl8211eg-vb only) figure 28. mii interface setup/hold time definitions figure 29 show an example of a packet transf er from mac to phy on the mii interface. txclk v ih(min) v il(max) txd[0:3] txen v ih(min) v il(max) t 4 t 3 t 1 t 2 figure 29. mii transmission cycle timing table 62. mii transmission cycle timing symbol description minimum typical maximum unit 100mbps 40 50 60 % t 1, t 2 txclk duty cycle 10mbps 40 50 60 % 100mbps - 40 - ns t 3 txclk period 10mbps - 400 - ns 100mbps 0 - 25 ns t 4 txen, txd[0:3] hold after txclk rising edge 10mbps 0 - 25 ns
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 61 track id: jatr-3375-16 rev. 1. 6 10.6.3. mii reception cycle timing (rtl8211eg-vb only) figure 30 show an example of a packet transf er from phy to mac on the mii interface. rxclk rxd[0:3] rxdv rxer v ih(min) v il(max) v ih(min) v il(max) t 4 t 5 t 1 t 3 t 2 figure 30. mii reception cycle timing table 63. mii reception cycle timing symbol description minimum typical maximum unit 100mbps 40 50 60 % t 1, t 2 rxclk duty cycle 10mbps 40 50 60 % 100mbps - 40 - ns t 3 rxclk period 10mbps - 400 - ns 100mbps 10 - - ns t 4 rxer, rxdv, rxd[0:3] setup to rxclk rising edge 10mbps 10 - - ns 100mbps 10 - - ns t 5 rxer, rxdv, rxd[0:3] hold after rxclk rising edge 10mbps 10 - - ns
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 62 track id: jatr-3375-16 rev. 1. 6 10.6.4. gmii timing modes (rtl8211eg-vb only) rxclk, gtxclk rxd[7:0], rxdv, rxer, txd[7:0], txen vih vih vil vil tgcc tgch tgcl tgsut tgsur tghtt tghtr tr tf figure 31. gmii timing table 64. gmii timing parameters symbol description min typical max units tgcc rxclk cycle time 7.5 8 8.5 ns tgch gtxclk, rxclk high time 2.5 - - ns tgcl gtxclk, rxclk low time 2.5 - - ns tr gtxclk, rxclk rise time - - 1 ns tf gtxclk, rxclk fall time - - 1 ns tgsut rxd, rxdv, rxer setup to of rxclk 2.5 - - ns tghtt rxd, rxdv, rxer hold from of rxclk 0.5 - - ns tgsur txd, txen setup to of gtxclk 2 - - ns tghtr txd, txen hold from of gtxclk 0 - - ns
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 63 track id: jatr-3375-16 rev. 1. 6 10.6.5. rgmii timing modes timing for this interface will be such that the clock a nd data are generated simultaneously by the source of the signals and therefore skew between the clock and data is critical to proper operation. figure 32 shows the effect of adding an internal delay to txc when in rgmii mode. figure 32. rgmii timing modes (for txc)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 64 track id: jatr-3375-16 rev. 1. 6 figure 33 shows the effect of adding an internal delay to the rxc flow when in rgmii mode. figure 33. rgmii timing modes (for rxc)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 65 track id: jatr-3375-16 rev. 1. 6 table 65. rgmii timing parameters symbol description min typical max units tgcc clock cycle duration (giga) 7.2 8 8.8 ns clock cycle duration (100mbps) 36 40 44 ns clock cycle duration (10mbps) 360 400 440 ns duty_g duty cycle for gigabit 45 50 55 % duty_t duty cycle for 10/100t 40 50 60 % tr rxc rise time (20%~80%) - - 0.75 ns tf rxc fall time (20%~80%) - - 0.75 ns tsetupt data to clock output setup (at transmitter integrated delay) 1.2 2 - ns tholdt data to clock output hold (at transmitter integrated delay) 1.2 2 - ns tsetupr data to clock input setup (at receiver integrated delay) 1.0 2 - ns tholdr data to clock input hold (at receiver integrated delay) 1.0 2 - ns tskewt data to clock output skew (at transmitter) -0.5 0 0.5 ns tskewr data to clock input skew (at receiver) this implies that pc board design will require clocks to be routed such that an additional trace delay of greater than 1.5ns and less than 2.0ns will be added to the associated clock signal. 1 1.8 2.6 ns
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 66 track id: jatr-3375-16 rev. 1. 6 11. mechanical dimensions 11.1. rtl8211e-vb/rtl8211e-vl mechanical dimensions (48-pin qfn)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 67 track id: jatr-3375-16 rev. 1. 6 11.2. mechanical dimensions notes (rtl8211e-vb/rtl8211e-vl) symbol dimension in mm dimension in inch min nom max min nom max a 0.75 0.85 1.00 0.030 0.034 0.039 a 1 0.00 0.02 0.05 0.000 0.001 0.002 a 3 0.20ref 0.008ref b 0.15 0.20 0.25 0.006 0.008 0.010 d/e 6.00bsc 0.236bsc d2/e2 4.15 4.4 4.65 0.163 0.173 0.183 e 0.40bsc 0.016bsc l 0.30 0.40 0.50 0.012 0.016 0.020 note 1: controlling dimension: millimeter (mm). note 2: reference document: jedec mo-220.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 68 track id: jatr-3375-16 rev. 1. 6 11.3. rtl8211eg-vb mechanical dimensions (64-pin qfn)
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 69 track id: jatr-3375-16 rev. 1. 6 11.4. mechanical dimensions notes (rtl8211eg-vb) symbol dimension in mm dimension in inch min nom max min nom max a 0.75 0.85 1.00 0.030 0.034 0.039 a 1 0.00 0.02 0.05 0.000 0.001 0.002 a 2 0.55 0.65 0.80 0.022 0.026 0.032 a 3 0.20ref 0.008ref b 0.18 0.25 0.30 0.007 0.010 0.012 d/e 9.00bsc 0.354bsc d 1 /e 1 8.75bsc 0.344bsc d 2 /e 2 3.55 3.80 4.05 0.140 0.150 0.160 e 0.50bsc 0.020bsc l 0.30 0.40 0.50 0.012 0.016 0.020 0 o - 14 o 0 o - 14 o note 1: controlling dimension: millimeter (mm). note 2: reference document: jedec mo-220.
rtl8211e/rtl8211eg datasheet integrated 10/100/1000m ethernet transceiver 70 track id: jatr-3375-16 rev. 1. 6 12. ordering information table 66. ordering information part number package status rtl8211e-vb-cg 48-pin qfn with ?green? package (supports 3.3v or 2.5v signaling for rgmii/gmii) mp rtl8211e-vl-cg 48-pin qfn with ?green? package (supports 1.5/1.8v rgmii) mp RTL8211EG-VB-CG 64-pin qfn with ?green? package (supports 3.3v or 2.5v signaling for rgmii/gmii) mp note: see page 6 (rtl8211e-vb/rtl8211e-vl) & 7 (rtl8211eg-vb) for package identification. realtek semiconductor corp. headquarters no. 2, innovation road ii hsinchu science park, hsinchu 300, taiwan tel.: +886-3-578-0211 fax: +886-3-577-6047 www.realtek.com

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